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rgb dimming led flash mcu HT45F0060 revision: v1.00 date: july 19, 2017
rev. 1.00 2 july 19, 2017 rev. 1.00 3 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu table of contents eates cpu features ......................................................................................................................... 5 peripheral features ................................................................................................................. 5 general description ......................................................................................... 6 block diagram .................................................................................................. 6 pin assignment ................................................................................................ 7 pin description ................................................................................................ 8 absolute maximum ratings ............................................................................ 9 d.c. characteristics ......................................................................................... 9 a.c. characteristics ....................................................................................... 10 constant current characteristics ................................................................. 11 power on reset characteristics .................................................................... 11 system architecture ...................................................................................... 12 clocking and pipelining ......................................................................................................... 12 program counter ................................................................................................................... 13 stack ..................................................................................................................................... 14 arithmetic and logic unit C alu ........................................................................................... 14 flash program memory ................................................................................. 15 structure ................................................................................................................................ 15 special vectors ..................................................................................................................... 15 look-up table ........................................................................................................................ 15 table program example ........................................................................................................ 16 in circuit programming C icp ............................................................................................... 17 on-chip debug support C ocds ......................................................................................... 18 data memory .................................................................................................. 19 structure ................................................................................................................................ 19 general purpose data memory ............................................................................................ 19 special purpose data memory ............................................................................................. 20 special function register description ........................................................ 21 indirect addressing registers C iar0, iar1 ......................................................................... 21 memory pointers C mp0, mp1 .............................................................................................. 21 accumulator C acc ............................................................................................................... 22 program counter low register C pcl .................................................................................. 22 look-up table registers C tblp, tbhp, tblh ..................................................................... 22 status register C status .................................................................................................... 22 oscillators ...................................................................................................... 24 oscillator overview ............................................................................................................... 24 system clock confgurations ............................................................................................... 24 high speed internal rc oscillator C hirc .......................................................................... 24 internal 32khz oscillator C lirc .......................................................................................... 25
rev. 1.00 2 july 19, 2017 rev. 1.00 3 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu operating modes and system clocks ........................................................ 25 system clocks ..................................................................................................................... 25 system operation modes ...................................................................................................... 26 control register .................................................................................................................... 27 operating mode switching ................................................................................................... 28 standby current considerations .......................................................................................... 32 wake-up ................................................................................................................................ 32 watchdog timer ............................................................................................. 33 watchdog timer clock source .............................................................................................. 33 watchdog timer control register ......................................................................................... 33 watchdog timer operation ................................................................................................... 34 reset and initialisation .................................................................................. 35 reset functions .................................................................................................................... 35 reset initial conditions ........................................................................................................ 36 input/output ports ........................................................................................ 38 pull-high resistors ................................................................................................................ 38 port a wake-up ..................................................................................................................... 38 i/o port control registers ..................................................................................................... 39 pin-shared functions ............................................................................................................ 39 i/o pin structures .................................................................................................................. 41 programming considerations ............................................................................................... 42 timer modules C tm ...................................................................................... 43 introduction ........................................................................................................................... 43 tm operation ........................................................................................................................ 43 tm clock source ................................................................................................................... 43 tm interrupts ......................................................................................................................... 43 tm external pins ................................................................................................................... 44 programming considerations ................................................................................................ 44 compact type tm C ctm .............................................................................. 45 compact tm operation ......................................................................................................... 45 compact type tm register description ................................................................................ 45 compact type tm operating modes .................................................................................... 49 cascading transceiver interface .................................................................. 55 cascading transceiver interface register description ......................................................... 56 cascade rx function operation ........................................................................................... 62 cascade tx procedure ......................................................................................................... 66 constant current led driver ........................................................................ 67 interrupts ........................................................................................................ 69 interrupt registers ................................................................................................................. 69 interrupt operation ................................................................................................................ 72 multi-function interrupt .......................................................................................................... 73 time base interrupt ............................................................................................................... 73 cascade transceiver interface interrupt ............................................................................... 75
rev. 1.00 4 july 19, 2017 rev. 1.00 5 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu timer module interrupts ....................................................................................................... 75 interrupt wake-up function ................................................................................................... 75 programming considerations ................................................................................................ 76 application circuits ....................................................................................... 77 instruction set ................................................................................................ 78 introduction ........................................................................................................................... 78 instruction timing .................................................................................................................. 78 moving and transferring data ............................................................................................... 78 arithmetic operations ............................................................................................................ 78 logical and rotate operation ............................................................................................... 79 branches and control transfer ............................................................................................. 79 bit operations ....................................................................................................................... 79 table read operations ......................................................................................................... 79 other operations ................................................................................................................... 79 instruction set summary .............................................................................. 80 table conventions ................................................................................................................. 80 instruction defnition ..................................................................................... 82 package information ..................................................................................... 91 8-pin sop (150mil) outline dimensions ............................................................................... 92 8-pin dfn (2mm3mm) outline dimensions ........................................................................ 93 10-pin sop (150mil) outline dimensions ............................................................................. 94
rev. 1.00 4 july 19, 2017 rev. 1.00 5 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu features cpu features ? operating voltage: f sys = 8mhz: 2.2v~5.5v ? up to 0.5 s instruction cycle with 8mhz system clock at v dd = 5v ? power down and wake-up functions to reduce power consumption ? oscillators: internal high speed rc C hirc internal 32khz rc C lirc ? multi-mode operation: normal, slow, idle and sleep ? fully integrated internal 8 mhz oscillator requires no external components ? all instructions executed in one or two instruction cycles ? table read instructions ? 63 powerful instructions ? 2-level subroutine nesting ? bit manipulation instruction peripheral features ? flash program memory: 1k 14 ? ram data memory: 64 8 ? watchdog timer function ? 8 bidirectional i/o lines ? constant current led driver ? cascading transceiver interface ? three 10-bit ctms for time measure, compare match output and pwm output functions ? single time-base function for generation of fxed time interrupt signals ? package type: 8-pin sop/8-pin dfn(2 3)/10-pin sop
rev. 1.00 6 july 19, 2017 rev. 1.00 7 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu general description th e HT45F0060 device is an assp mcu dedicated for use in rgb dimming led control applications. it is a flash memory type 8-bit high performance risc architecture microcontroller. offering users the convenience of flash memory multi-programming features, the device also includes a wide range of functions and features. other memory includes an area of ram data memory . multiple extremely flexible timer module s provide timing, compare match output and pwm generation functions . protective features such as an internal watchdog timer coupled with excellent noise immunity and esd protection ensure that reliable operation is maintained in hostile electrical environments. a full choice of internal high speed and low speed oscillator functions are provided including a fully integrated system oscillator which requires no external components for its implementation. the ability to operate and switch dynamically between a range of operating modes using different clock sources gives users the ability to optimise microcontroller operation and minimi s e power consumption. the inclusion of flexible i/o programming features, time-base function along with many other features ensure that the device will find excellent use in applications such as breathing lights, christmas lights, light strips and mood lights etc. block diagram 8-bit risc mcu core i/o timer modules flash programming circuitry (icp/ocds) time base constant current cascading transceiver watchdog timer reset circuit internal rc oscillators ram data memory flash program memory
rev. 1.00 6 july 19, 2017 rev. 1.00 7 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu pin assignment 1 2 3 4 8 7 6 5 vdd pa2/[casdi]/icpck pa1/[casdo] pa0/icpda pa5/cco0 pa6/cco1 vss pa7/cco2 10 9 8 7 6 1 2 3 4 5 HT45F0060 8 sop-a/dfn-a vdd pa2/[casdi]/icpck pa1/[casdo] pa0/icpda pa3/casdi pa4/casdo vss pa7/cco2 pa6/cco1 pa5/cco0 HT45F0060 10 sop-a 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 ocdsck vdd pa2/[casdi]/icpck pa1/[casdo] pa0/icpda pa3/casdi nc nc ocdsda pa4/casdo vss pa7/cco2 pa6/cco1 pa5/cco0 nc nc ht45v0060 16 nsop-a note: 1. if the pin-shared pin functions have multiple outputs, the desired pin-shared function is determined by the corresponding software control bits. 2. the ocdsda and ocdsck pins are used as the ocds dedicated pins and only available for the ht45v0060 device which is the ocds ev chip of the HT45F0060.
rev. 1.00 8 july 19, 2017 rev. 1.00 9 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu pin description with the exception of the power pins, all pins on the device can be referenced by its port name, e.g. pa0, pa1 etc., which refer to the digital i/o function of the pins. however these port pins are also shared with other function such as the cascade transceiver interface pins etc. the function of each pin is listed in the following table, however the details behind how each pin is confgured is contained in other sections of the datasheet. pin name function opt i/t o/t description pa0/icpda pa0 papu pawu pas0 st cmos general purpose i/o. register enabled pull-high and wake-up. icpda st cmos icp address/data pa1/[casdo] pa1 papu pawu pas0 st cmos general purpose i/o. register enabled pull-high and wake-up. casdo pas0 cmos cascade transceiver interface output pa2/[casdi]/ icpck pa2 papu pawu pas0 st cmos general purpose i/o. register enabled pull-high and wake-up. casdi pas0 st cascade transceiver interface input icpck st icp clock pin pa3/ casdi pa3 papu pawu pas0 st cmos general purpose i/o. register enabled pull-high and wake-up. casdi pas0 st cascade transceiver interface input pa4 /casd o pa4 papu pawu pas1 st cmos general purpose i/o. register enabled pull-high and wake-up. casdo pas1 cmos cascade transceiver interface output pa5/cco0 pa5 papu pawu pas1 st cmos general purpose i/o. register enabled pull-high and wake-up. cco0 pas1 cmos led pwm constant current output pa6/cco1 pa6 papu pawu pas1 st cmos general purpose i/o. register enabled pull-high and wake-up. cco1 pas1 cmos led pwm constant current output pa7/cco2 pa7 papu pawu pas1 st cmos general purpose i/o. register enabled pull-high and wake-up. cco2 pas1 cmos led pwm constant current output vdd vdd pwr power supply vss vss pwr ground the following pins are only for the ht45v0060 nc nc no connection ocdsda ocdsda st cmos ocds address/data, for ev chip only ocdsck ocdsck st ocds clock pin, for ev chip only legend: i/t: input type; o/t: output type; op: optional by register option; pwr: power; st: schmitt trigger input; cmos: cmos output
rev. 1.00 8 july 19, 2017 rev. 1.00 9 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu absolute maximum ratings supply voltage ................................................................................................ v ss ?0.3v to v ss +6.0v input voltage .................................................................................................. v ss ? 0.3v to v dd +0.3v storage temperature .................................................................................................... -50 ? c to 125?c operating temperature .................................................................................................. -40 ? c to 85 ? c i ol total ..................................................................................................................................... 80ma i oh total .................................................................................................................................... - 80ma total power dissipation ......................................................................................................... 500mw note: these are stress ratings only. stresses exceeding the range specified under "absolute maximum ratings" may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specifcation is not implied and prolonged exposure to extreme conditions may affect device reliability. d.c. characteristics ta = 25c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage (hirc) f sys = f hirc = 8mhz 2.2 5.5 v operating current (lirc) 3v no load, all peripherals off, f sys = f lirc = 32khz 10 20 5v 30 50 operating current (hirc) 3v no load, all peripherals off, f sys = f hirc = 8mhz 1.0 2.0 ma 5v 2.0 3.0 ma 3v no load, all peripherals off, f sys = f hirc /2 , f hirc = 8mhz 1.0 1.5 ma 5v 1.5 2.0 ma 3v no load, all peripherals off, f sys = f hirc /4 , f hirc = 8mhz 0.9 1.3 ma 5v 1.3 1.8 ma 3v no load, all peripherals off, f sys = f hirc /8 , f hirc = 8mhz 0.8 1.1 ma 5v 1.1 1.6 ma 3v no load, all peripherals off, f sys = f hirc /16 , f hirc = 8mhz 0.7 1.0 ma 5v 1.0 1.4 ma 3v no load, all peripherals off, f sys = f hirc /32 , f hirc = 8mhz 0.6 0.9 ma 5v 0.9 1.2 ma 3v no load, all peripherals off, f sys = f hirc /64 , f hirc = 8mhz 0.5 0.8 ma 5v 0.8 1.1 ma i stb standby current (sleep mode) 3v no load, all peripherals off, wdt off 0.2 0.8 5v 0.5 1 standby current (sleep mode) 3v no load, all peripherals off, wdt on 1.3 5.0 5v 2.2 10 standby current (idle0 mode) 3v no load, all peripherals off, f sub on 1.3 3.0 5v 5.0 10 standby current (idle1 mode, hirc) 3v no load, all peripherals off, f sub on, f sys = f hirc = 8mhz 0.8 1.6 ma 5v 1.0 2.0 ma v il input low voltage for i/o ports or input pins 5v 0 1.5 v 0 0.2v dd v ih input high voltage for i/o ports or input pins 5v 3.5 5 v 0.8v dd v dd
rev. 1.00 10 july 19, 2017 rev. 1.00 11 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu symbol parameter test conditions min. typ. max. unit v dd conditions i ol sink current for i/o pins 3v v ol = 0.1v dd 15.5 31 ma 5v 31 62 i oh source current for i/o pins 3v v oh = 0.9v dd -3.5 -7.0 ma 5v -7.2 -14.5 r ph pull-high resistance for i/o ports 3v 20 60 100 k 5v 10 30 50 i leak input leakage current 5v v in = v dd or v in = v ss 1 a i ocds operating current, used for ocds ev and connected to e-link, normal mode, f sys = f hirc 3v no load, f hirc = 8mhz, wdt enable 1.4 2.0 ma a.c. characteristics ta = 25c symbol parameter test conditions min. typ. max. unit v dd conditions f sys system clock (hirc) 2.2v~ 5.5v f sys = f hirc = 8mhz 8 mhz system clock (lirc) 2.2v~ 5.5v f sys = f lirc = 32khz 32 khz f hirc high speed internal rc oscillator (hirc) 3v / 5v ta = 25c -2% 8 +2% mhz 3v / 5v ta = 0c~70c -5% 8 +5% mhz 2.2v~ 5.5v ta = 0c~70c -8% 8 +8% mhz 2.2v~ 5.5v ta = -40c~85c -12% 8 +12% mhz f lirc low speed internal rc oscillator (lirc) 2.2v~5.5v ta = -40c~ 85c 8 32 50 khz t rstd system reset delay time (power-on reset, wdt software reset) 25 50 100 ms system reset delay time (wdt time-out hardware cold reset) 8.3 16.7 33.3 ms t sst system start-up time (wake-up from condition where f sys is off) f sys = f hirc ~ f hirc /64 16 t hirc f sys = f sub = f lirc 2 t lirc system start-up time (wake-up from condition where f sys is on) f sys = f hirc ~ f hirc /64, f h = f hirc 2 t h f sys = f sub = f lirc 2 t sub system speed switch time (slow mode ? normal mode) f hirc off on (hircf = 1) 16 t hirc t sreset minimum software reset width to reset 45 90 250 s t casdi casdi input pin minimum pulse width 0.3 s f casclki casclki maximum clock source frequency 5v 8 mhz 1rwhw sys i sys dd dud i ud du iut d s dsdu 9d 9dddyds
rev. 1.00 10 july 19, 2017 rev. 1.00 11 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu constant current characteristics operating temperature: -40c~85c, unless otherwise specify symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage 2.7 5.5 v i ccs additional current for constant current function enable 5v ccon=off 5 6.5 ma 3v ccon=off 3.8 5 ma i cco ccon output sink current 5v current range, v ccon =1.5v ccg[1:0]=00 -5% 5 +5% ma current range, v ccon =1.5v ccg[1:0]=01 -10% 15 +10% ma current range, v ccon =1.5v ccg[1:0]=10 -15% 35 +15% ma current range, v ccon =1.5v ccg[1:0]=11 -20% 60 +20% ma di cco1 current skew (channel) 3v/5v i ccon =5ma, v ccon =0.7v 1.5 3 % di cco2 current skew (ic) 5v/3v i ccon =5ma, v ccon =0.7v 3 6 % %/dv cco output current vs. output voltage regulation 5v/3v v ccon =0.7v~3.0v, i ccon =5ma 0.1 %/v %/dv dd output current vs. supply voltage regulation v dd =2.7v~5.5v, v ccon =0.7v 1.0 8.0 %/v note: %/dv cco = {[i ccon (at v ccon =3.0v) - i ccon (at v ccon =0.7v)]/i ccon (at v ccon =1.5v)} 100%/(3.0vC0.7v) %/dv dd = {[i ccon (at v dd =5.5v) - i ccon (at v dd =2.7v)]/i ccon (at v dd =4.0v)} 100% /(5.5vC2.7v) power on reset characteristics ta = 25c symbol parameter test conditions min. typ. max. unit v dd conditions v por v dd start voltage to ensure power-on reset 100 mv rr por v dd rising rate to ensure power-on reset 0.035 v/ms t por minimum time for v dd stays at v por to ensure power-on reset 1 ms v dd t por rr por v por time
rev. 1.00 12 july 19, 2017 rev. 1.00 13 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu system architecture a key factor in the high-performance features of the holtek range of microcontrollers is attributed to their internal system architecture. the device take s advantage of the usual features found within risc microcontrollers providing increased speed of operation and enhanced performance. the pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. an 8-bit wide alu is used in practically all instruction set operations, which carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. the internal data path is simplified by moving data through the accumulator and the alu. certain internal registers are implemented in the data memory and can be directly or indirectly addressed. the simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional i/o control system with maximum reliability and fexibility. this makes the device suitable for low-cost, high-volume production for controller applications. clocking and pipelining the main system clock, derived from either a hirc or lirc oscillator is subdivided into four internally generated non-overlapping clocks, t1~t4. the program counter is incremented at the beginning of the t1 clock during which time a new instruction is fetched. the remaining t2~t4 clocks carry out the decoding and execution functions. in this way, one t1~t4 clock cycle forms one instruction cycle. although the fetching and execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. the exception to this are instructions where the contents of the program counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. fetch inst. (pc+2) execute inst. (pc+1) oscillator clock (system clock) phase clock t1 phase clock t2 phase clock t3 phase clock t4 program counter pipelining pc pc+1 pc+2 fetch inst. (pc+1) execute inst. (pc) execute inst. (pc-1) fetch inst. (pc) system clocking and pipelining for instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. an extra cycle is required as the program takes one cycle to frst obtain the actual jump or call address and then another cycle to actually execute the branch. the requirement for this extra cycle should be taken into account by programmers in timing sensitive applications.
rev. 1.00 12 july 19, 2017 rev. 1.00 13 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu execute inst. 1 fetch inst. 2 1 mov a, [12h] 2 call delay 3 cpl [12h] 4: 5: 6 delay: nop fetch inst. 1 execute inst. 2 fetch inst. 3 flush pipeline fetch inst. 6 execute inst. 6 fetch inst. 7 instruction fetching program counter during program execution, the program counter is used to keep track of the address of the next instruction to be executed. it is automatically incremented by one each time an instruction is executed except for instructions, such as "jmp" or "call" that demands a jump to a non- consecutive program memory address. only the lower 8 bits, known as the program counter low register, are directly addressable by the application program. when executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the program counter. for conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. program counter program counter high byte pcl register pc9~pc8 pcl7~pcl0 program counter the lower byte of the program counter, known as the program counter low register or pcl, is available for program control and is a readable and writeable register. by transferring data directly into this register, a short program jump can be executed directly. however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory that is 256 locations. when such program jumps are executed it should also be noted that a dummy cycle will be inserted. manipulating the pcl register may cause program branching, so an extra cycle is needed to pre-fetch.
rev. 1.00 14 july 19, 2017 rev. 1.00 15 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu stack this is a special part of the memory which is used to save the contents of the program counter only. the stack is organized into 2 levels and neither part of the data nor part of the program space, and is neither readable nor writeable. the activated level is indexed by the stack pointer, and is neither readable nor writeable. at a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction, ret or reti, the program counter is restored to its previous value from the stack. after a device reset, the stack pointer will point to the top of the stack. if the stack is full and an enabled interrupt takes place, the interrupt request fag will be recorded but the acknowledge signal will be inhibited. when the stack pointer is decremented, by ret or reti, the interrupt will be serviced. this feature prevents stack overfow allowing the programmer to use the structure more easily. however, when the stack is full, a call subroutine instruction can still be executed which will result in a stack overfow. precautions should be taken to avoid such cases which might cause unpredictable program branching. if the stack is overfow, the frst program counter save in the stack will be lost. stack pointer stack level 2 stack level 1 program memory program counter bottom of stack top of stack arithmetic and logic unit C alu the arithmetic-logic unit or alu is a critical area of the microcontroller that carries out arithmetic and logic operations of the instruction set. connected to the main microcontroller data bus, the alu receives related instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specifed register. as these alu calculation or operations may result in carry, borrow or other status changes, the status register will be correspondingly updated to refect these changes. the alu supports the following functions: ? arithmetic operations: add, addm, adc, adcm, sub, subm, sbc, sbcm, daa ? logic operations: and, or, xor, andm, orm, xorm, cpl, cpla ? rotation: rra, rr, rrca, rrc, rla, rl, rlca, rlc ? increment and decrement: inca, inc, deca, dec ? branch decision: jmp, sz, sza, snz, siz, sdz, siza, sdza, call, ret, reti
rev. 1.00 14 july 19, 2017 rev. 1.00 15 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu flash program memory the program memory is the location where the user code or program is stored. for this device the program memory is flash type, which means it can be programmed and re-programmed a large number of times, allowing the user the convenience of code modifcation on the same device. by using the appropriate programming tools, the flash device offer users the fexibility to conveniently debug and develop their applications while also offering a means of field programming and updating. structure the program memory has a capacity of 1k14 bits. the program memory is addressed by the program counter and also contains data, table information and interrupt entries. table data, which can be setup in any location within the program memory, is addressed by a separate table pointer register. 000h 004h 014h 3ffh reset interrupt vectors 14 bits look-up table n00h nffh program memory structure special vectors within the program memory, certain locations are reserved for the reset and interrupts. the location 000h is reserved for use by the device reset for program initialisation. after a device reset is initiated, the program will jump to this location and begin execution. look-up table any location within the program memory can be defned as a look-up table where programmers can store fxed data. to use the look-up table, the table pointer must frst be setup by placing the address of the look up data to be retrieved in the table pointer registers, tblp and tbhp. these registers defne the total address of the look-up table. after setting up the table pointer, the table data can be retrieved from the program memory using the "tabrd [m]" or "tabrdl[m]" instructions respectively . when the instruction is executed, the lower order table byte from the program memory will be transferred to the user defined data memory register [m] as specified in the instruction. the higher order table data byte from the program memory will be transferred to the tblh special register. any unused bits in this transferred higher order byte will be read as "0". the accompanying diagram illustrates the addressing data fow of the look-up table.
rev. 1.00 16 july 19, 2017 rev. 1.00 17 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu last page or tbhp register tblp register program memory register tblh user selected register address data 14 bits high byte low byte table program example the following example shows how the table pointer and table data is defned and retrieved from the microcontroller. this example uses raw table data located in the program memory which is stored there using the org statement. the value at this org statement is "300h" which refers to the start address of the last page within the 1k words program memory of the device. the table pointer low byte register is setup here to have an initial value of "06h". this will ensure that the frst data read from the data table will be at the program memory address "306h" or 6 locations after the start of the last page. note that the value for the table pointer is referenced to the specifc address pointed by the tblp and tbhp registers if the "tabrd [m]" instruction is being used. the high byte of the table data which in this case is equal to zero will be transferred to the tblh register automatically when the "tabrd [m] instruction is executed. because the tblh register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and interrupt service routine use table read instructions. if using the table read instructions, the interrupt service routines may change the value of the tblh and subsequently cause errors if used again by the main routine. as a rule it is recommended that simultaneous use of the table read instructions should be avoided. however, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. note that all table related instructions require two instruction cycles to complete their operation. table read program example ds .section data tempreg1 db? ; temporary register #1 tempreg2 db? ; temporary register #2 code0 .section code mov a,06h ; initialise table pointer - note that this address is referenced mov tblp,a ; to the last page or the page that tbhp pointed mov a,03h ; initialise high table pointer mov tbhp,a ; it is not necessary to set tbhp if executing tabrdl : tabrd tempreg1 ; transfers value in table referenced by table pointer ; data at program memory address "306h" transferred to tempreg1 and tblh dec tblp ; reduce value of table pointer by one tabrd tempreg2 ; transfers value in table referenced by table pointer ; data at program memory address "305h" transferred to tempreg2 and tblh ; in this example the data "1ah" is transferred to tempreg1 and data "0fh" ; to tempreg2 ; the value "00h" will be transferred to the high byte register tblh : org 300h ; sets initial address of last page dc 00ah,00bh,00ch,00dh,00eh,00fh,01ah,01bh :
rev. 1.00 16 july 19, 2017 rev. 1.00 17 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu in circuit programming C icp the provision of flash type program memory provides the user with a means of convenient and easy upgrades and modifcations to their programs on the same device. as an additional convenience, holtek has provided a means of programming the microcontroller in- circuit using a 4-pin interface. this provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller, and then programming or upgrading the program at a later stage. this enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and re- insertion of the device. holtek writer pins mcu programming pins pin description icpda pa0 programming serial data/address icpck pa2 programming clock vdd vdd power supply vss vss ground the program memory can be programmed serially in-circuit using this 4-wire interface. data is downloaded and uploaded serially on a single pin with an additional line for the clock. two additional lines are required for the power supply. the technical details regarding the in-circuit programming of the device are beyond the scope of this document and will be supplied in supplementary literature. during the programming process, the user can tak e care of the icpda and icpck pins for data and clock programming purposes to ensure that no other outputs are connected to these two pins. writer_vdd icpda icpck writer_vss to other circuit vdd pa0 pa2 vss writer connector signals mcu programming pins * * note: * may be resistor or capacitor. the resistance of * must be greater than 1k or the capacitance of * must be less than 1nf.
rev. 1.00 18 july 19, 2017 rev. 1.00 19 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu on-chip debug support C ocds there is an ev chip named ht45v0060 which is used to emulate the real mcu device named HT45F0060 . the ev chip device also provides an "on-chip debug" function to debug the real mcu device during the development process. the ev chip and the real mcu device are almost functionally compatible except for "on-chip debug" function. users can use the ev chip device to emulate the real chip device behavior by connecting the ocdsda and ocdsck pins to the holtek ht-ide development tools. the ocdsda pin is the ocds data/address input/output pin while the ocdsck pin is the ocds clock input pin. when users use the ev chip for debugging, other functions which are shared with the ocdsda and ocdsck pins in the device will have no effect in the ev chip. for more detailed ocds information, refer to the corresponding document named "holtek e-link for 8-bit mcu ocds users guide". holtek e-link pins ev chip pins pin description ocdsda ocdsda on-chip debug support data/address input/output ocdsck ocdsck on-chip debug support clock input vdd vdd power supply vss vss ground
rev. 1.00 18 july 19, 2017 rev. 1.00 19 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu data memory the data memory is a volatile area of 8-bit wide ram internal memory and is the location where temporary information is stored. categorised into two types, the frst of these is an area of ram, known as the special function data memory. these registers have fxed locations and are necessary for correct operation of the devices. many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. the second area of data memory is known as the general purpose data memory, which is reserved for general purpose use. all locations within this area are read and write accessible under program control. switching between the different data memory banks must be achieved by properly setting the memory pointers to correct value. structure the data memory has a bank, which is implemented in 8-bit wide memory. the data memory bank is categorized into two types, the special purpose data memory and the general purpose data memory. the address range of the special purpose data memory for the device is from 00h to 3fh while the general purpose data memory address range is from 40h to ffh. special purpose data memory general purpose data memory located banks bank: address capacity bank: address 0 0: 00h~3fh 64 8 0: 40h~f fh data memory summary 00h 3fh 40h ffh special purpose data memory general purpose data memory bank 0 (bank 0) (bank 0) data memory structure general purpose data memory all microcontroller programs require an area of read/write memory where temporary data can be stored and retrieved for use later. it is this area of ram memory that is known as general purpose data memory. this area of data memory is fully accessible by the user programing for both reading and writing operations. by using the bit operation instructions individual bits can be set or reset under program control giving the user a large range of fexibility for bit manipulation in the data memory.
rev. 1.00 20 july 19, 2017 rev. 1.00 21 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu special purpose data memory this area of data memory is where registers, necessary for the correct operation of the microcontroller, are stored. most of the registers are both readable and writeable but some are protected and are readable only, the details of which are located under the relevant special function register section. note that for locations that are unused, any read instruction to these addresses will return the value "00h". 00h iar0 01h mp0 02h iar1 03h mp1 04h 05h acc 06h pcl 07h tblp 08h tblh 09h rstfc 0ah status 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 19h 18h 1bh 1ah 1dh 1ch 1fh 1eh 13h 14h 15h 16h 17h hircc papu pawu 20h 21h 22h 29h 28h 2ah 2bh 23h 24h 25h 26h 27h ctm1c1 pa pac ctm1c0 pas0 intc0 intc1 mfi0 wdtc tbc ctm0dh ctm0c1 ctm0c0 ctm0dl ctm0ah bank 0 bank0 2eh 30h 31h 32h 33h 34h 35h 36h 37h 38h 3fh ctm0al 2ch 2dh : unused, read as 00 2fh pscr scc tbhp mfi1 mfi2 pas1 ifs ctm2c1 ctm1dl casd2 casth d0cnt cascon caspre ccs ctm2dl ctm2dh ctm2al pcnt casd0 rcnt casd1 ctm2ah intcon ctm1ah ctm1al ctm1dh ctm2c0 d1cnt special purpose data memory
rev. 1.00 20 july 19, 2017 rev. 1.00 21 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu special function register description most of the special function register details will be described in the relevant functional section, however several registers require a separate description in this section. indirect addressing registers C iar0, iar1 the indirect addressing registers, iar0 and iar1, although having their locations in normal ram register space, do not actually physically exist as normal registers. the method of indirect addressing for ram data manipulation uses these indirect addressing registers and memory pointers, in contrast to direct memory addressing, where the actual memory address is specifed. actions on the iar0 and iar1 registers will result in no actual read or write operation to these registers but rather to the memory location specifed by their corresponding memory pointers, mp0 or mp1. acting as a pair, iar0 and mp0 can together access data from bank 0 while the iar1 register together with the mp1 register can access data from any data memory bank. as the indirect addressing registers are not physically implemented, reading the indirect addressing registers will return a result of "00h" and writing to the registers will result in no operation. memory pointers C mp0, mp1 two memory pointers, known as mp0 and mp1 are provided. these memory pointers are physically implemented in the data memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. when any operation to the relevant indirect addressing registers is carried out, the actual address that the microcontroller is directed to is the address specifed by the related memory pointer. mp0, together with indirect addressing register, iar0, are used to access data from bank 0, while mp1 together with iar1 are used to access data from all banks. the following example shows how to clear a section of four data memory locations already defned as locations adres1 to adres4. indirect addressing program example data .section data adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 code org 00h start: mov a,04h ; setup size of block mov block,a mov a,offset adres1 ; accumulator loaded with frst ram address mov mp0,a ; setup memory pointer with frst ram address loop : clr iar0 ; clear the data at address defned by mp0 inc mp0 ; increment memory pointer sdz block ; check if last memory location has been cleared jmp loop continue : the important point to note here is that in the example shown above, no reference is made to specifc data memory addresses.
rev. 1.00 22 july 19, 2017 rev. 1.00 23 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu accumulator C acc the accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the alu. the accumulator is the place where all intermediate results from the alu are stored. without the accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the data memory resulting in higher programming and timing overheads. data transfer operations usually involve the temporary storage function of the accumulator; for example, when transferring data between one user-defined register and another, it is necessary to do this by passing the data through the accumulator as no direct transfer between two registers is permitted. program counter low register C pcl to provide additional program control functions, the low byte of the program counter is made accessible to programmers by locating it within the special purpose area of the data memory. by manipulating this register, direct jumps to other program locations are easily implemented. loading a value directly into this pcl register will cause a jump to the specifed program memory location, however, as the register is only 8-bit wide, only jumps within the current program memory page are permitted. when such operations are used, note that a dummy cycle will be inserted. look-up table registers C tblp, tbhp, tblh these three special function registers are used to control operation of the look-up table which is stored in the program memory. tblp and tbhp are the table pointers and indicate the location where the table data is located. their value must be setup before any table read commands are executed. their value can be changed, for example using the "inc" or "dec" instructions, allowing for easy table data pointing and reading. tblh is the location where the high order byte of the table data is stored after a table read data instruction has been executed. note that the lower order table data byte is transferred to a user defned location. status register C status this 8-bit register contains the zero fag (z), carry fag (c), auxiliary carry fag (ac), overfow fag (ov), power down fag (pdf), and watchdog time-out fag (to). these arithmetic/logical operation and system management fags are used to record the status and operation of the microcontroller. with the exception of the to and pdf fags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the to or pdf fag. in addition, operations related to the status register may give different results due to the different instruction operations. the to fag can be affected only by a system power-up, a wdt time-out or by executing the "clr wdt" or "halt" instruction. the pdf fag is affected only by executing the "halt" or "clr wdt" instruction or during a system power-up. the z, ov, ac, and c fags generally refect the status of the latest operations. ? c is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. c is also affected by a rotate through carry instruction. ? ac is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. ? z is set if the result of an arithmetic or logical operation is zero; otherwise z is cleared. ? ov is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared.
rev. 1.00 22 july 19, 2017 rev. 1.00 23 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu ? pdf is cleared by a system power-up or executing the "clr wdt" instruction. pdf is set by executing the "halt" instruction. ? to is cleared by a system power-up or executing the "clr wdt" or "halt" instruction. to is set by a wdt time-out. in addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. if the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. ? status register bit 7 6 5 4 3 2 1 0 name to pdf ov z ac c r/w r r r/w r/w r/w r/w por 0 0 x x x x "x": unknown bit 7~6 unimplemented, read as "0" bit 5 to : watchdog time-out fag 0: after power up or executing the "clr wdt" or "halt" instruction 1: a watchdog time-out occurred. bit 4 pdf : power down fag 0: after power up or executing the "clr wdt" instruction 1: by executing the "halt" instruction bit 3 ov : overfow fag 0: no overfow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. bit 2 z : zero fag 0: the result of an arithmetic or logical operation is not zero 1: the result of an arithmetic or logical operation is zero bit 1 ac : auxiliary fag 0: no auxiliary carry 1: an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction bit 0 c : carry fag 0: no carry-out 1: an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation c is also affected by a rotate through carry instruction.
rev. 1.00 24 july 19, 2017 rev. 1.00 25 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu oscillators various oscillator options offer the user a wide range of functions according to their various application requirements. the flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. oscillator selections and operation are selected through the application program and relevant control registers. oscillator overview in addition to being the source of the main system clock the oscillators also provide clock sources for the watchdog timer and time base interrupts. two fully integrated internal oscillators, requiring no external components, are provided to form a range of both fast and slow system oscillators. the higher frequency oscillator provides higher performance but carry with it the disadvantage of higher power requirements, while the opposite is of course true for the lower frequency oscillator. with the capability of dynamically switching between fast and slow system clock, the device has the fexibility to optimize the performance/power ratio, a feature especially important in power sensitive portable applications. type name frequency internal high speed rc hirc 8mhz internal low speed rc lirc 32khz oscillator types system clock confgurations there are two oscillator sources, a high speed oscillator and a low speed oscillator. the high speed oscillator is the internal 8mhz rc oscillator, hirc. the low speed oscillator is the internal 32khz rc oscillator, lirc. the frequency of the slow speed or high speed system clock is also determined using the cks2~cks0 bits in the scc register. note that two oscillator selections must be made namely one high speed and one low speed system oscillators. it is not possible to choose a no-oscillator selection for either the high or low speed oscillator. hircen prescaler high speed oscillator low speed oscillator f h /2 f h /16 f h /64 f h /8 f h /4 f h /32 cks2~ cks0 f sys f sub f sub lirc f lirc f lirc hirc f h idle0 sleep idle2 sleep system clock confgurations high speed internal rc oscillator C hirc the high speed internal rc oscillator is a fully integrated system oscillator requiring no external components. the internal rc oscillator has a fxed frequency of 8mhz. device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised.
rev. 1.00 24 july 19, 2017 rev. 1.00 25 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu internal 32khz oscillator C lirc the internal 32khz system oscillator is a fully integrated rc oscillator with a typical frequency of 32khz at 5v, requiring no external components for its implementation. device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. operating modes and system clocks present day applications require that their microcontrollers have high performance but often still demand that they consume as little power as possible, conficting requirements that are especially true in battery powered portable applications. the fast clocks required for high performance will by their nature increase current consumption and of course vice-versa, lower speed clocks reduce current consumption. as holtek has provided the device with both high and low speed clock sources and the means to switch between them dynamically, the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. system clocks the device has many different clock sources for both the cpu and peripheral function operation. by providing the user with a wide range of clock selections using register programming, a clock system can be confgured to obtain maximum application performance. the main system clock, can come from either a high frequency, f h , or low frequency, f sub , source, and is selected using the cks2~cks0 bits in the scc register. the high speed system clock is sourced from hirc oscillator. the low speed system clock source can be sourced from the lirc oscillator. the other choice, which is a divided version of the high speed system oscillator has a range of f h /2~f h /64. hircen prescaler high speed oscillator low speed oscillator f h /2 f h /16 f h /64 f h /8 f h /4 f h /32 cks2~ cks0 f sys f sub f sub lirc f lirc f lirc hirc f h wdt f sys /4 time base f sub f sys prescaler clksel[1:0] f psc idle0 sleep idle2 sleep tb[2:0] device clock confgurations note: when the system clock source f sys is switched to f sub from f h , the high speed oscillator can be stopped to conserve the power or continue to oscillate to provide the clock source, f h ~f h /64, for peripheral circuit to use, which is determined by confguring the corresponding high speed oscillator enable control bit.
rev. 1.00 26 july 19, 2017 rev. 1.00 27 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu system operation modes there are six different modes of operation for the microcontroller, each one with its own special characteristics and which can be chosen according to the specific performance and power requirements of the application. there are two modes allowing normal operation of the microcontroller, the normal mode and slow mode. the remaining four modes, the sleep, idle0, idle1 and idle2 mode are used when the microcontroller cpu is switched off to conserve power. operation mode cpu related register value f sys f h f sub f lirc fhiden fsiden cks[2:0] normal mode on x x 000~110 on on on on slow mode on x x 111 on on/off (1) on on idle0 mode off 0 1 000~110 off off on on 111 on idle1 mode off 1 1 xxx on on on on idle2 mode off 1 0 000~110 on on off on 111 off sleep mode off 0 0 xxx off off off on/off (2) "x ": dont care note: 1. the f h clock will be switched on or off by confguring the corresponding oscillator enable bit in the slow mode. 2. the f lirc clock can be switched on or off which is controlled by the wdt function being enabled or disabled in the sleep mode. normal mode as the name suggests this is one of the main operating modes where the microcontroller has all of its functions operational and where the system clock is provided by one of the high speed oscillator. this mode operates allowing the microcontroller to operate normally with a clock source will come from the high speed oscillator, hirc. the high speed oscillator will however frst be divided by a ratio ranging from 1 to 64, the actual ratio being selected by the cks2~cks0 bits in the scc register. although a high speed oscillator is used, running the microcontroller at a divided clock ratio reduces the operating current. slow mode this is also a mode where the microcontroller operates normally although now with a slower speed clock source. the clock source used will be from f sub . the f sub clock is derived from the lirc oscillator. sleep mode the sleep mode is entered when an halt instruction is executed and when the fhiden and fsiden bit are low. in the sleep mode the cpu will be stopped, and the f sub clock to peripheral will be stopped too. however the f lirc clock can still continue to operate if the wdt function is enabled. idle0 mode the idle0 mode is entered when an halt instruction is executed and when the fhiden bit in the scc register is low and the fsiden bit in the scc register is high. in the idle0 mode the cpu will be switched off but the low speed oscillator will be turned on to drive some peripheral functions.
rev. 1.00 26 july 19, 2017 rev. 1.00 27 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu idle1 mode the idle1 mode is entered when an halt instruction is executed and when the fhiden bit in the scc register is high and the fsiden bit in the scc register is high. in the idle1 mode the cpu will be switched off but both the high and low speed oscillators will be turned on to provide a clock source to keep some peripheral functions operational. idle2 mode the idle2 mode is entered when an halt instruction is executed and when the fhiden bit in the scc register is high and the fsiden bit in the scc register is low. in the idle2 mode the cpu will be switched off but the high speed oscillator will be turned on to provide a clock source to keep some peripheral functions operational. control register the registers, scc and hircc, are used to control the system clock and the corresponding oscillator confgurations. register name bit 7 6 5 4 3 2 1 0 scc cks2 cks1 cks0 fhiden fsiden hircc hircf hircen system operating mode control registers list ? scc register bit 7 6 5 4 3 2 1 0 name cks2 cks1 cks0 fhiden fsiden r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7~5 cks2~cks0 : system clock selection 000: f h 001: f h /2 010: f h /4 011: f h /8 100: f h /16 101: f h /32 110: f h /64 111: f sub these three bits are used to select which clock is used as the system clock source. in addition to the system clock source directly derived from f h or f sub , a divided version of the high speed system oscillator can also be chosen as the system clock source. bit 4~2 unimplemented, read as "0" bit 1 fhiden : high frequency oscillator control when cpu is switched off 0: disable 1: enable this bit is used to control whether the high speed oscillator is activated or stopped when the cpu is switched off by executing an "halt" instruction. bit 0 fsiden : low frequency oscillator control when cpu is switched off 0: disable 1: enable this bit is used to control whether the low speed oscillator is activated or stopped when the cpu is switched off by executing an "halt" instruction.
rev. 1.00 28 july 19, 2017 rev. 1.00 29 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu ? hircc register bit 7 6 5 4 3 2 1 0 name hircf hircen r/w r/w r/w por 0 1 bit 7~2 unimplemented, read as "0" bit 1 hircf : hirc oscillator stable fag 0: unstable 1: stable this bit is used to indicate whether the hirc oscillator is stable or not. when the hircen bit is set to 1 to enable the hirc oscillator, the hircf bit will first be cleared to 0 and then set to 1 after the hirc oscillator is stable. bit 0 hircen : hirc oscillator enable control 0: disable 1: enable operating mode switching the device can switch between operating modes dynamically allowing the user to select the best performance/power ratio for the present task in hand. in this way microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. in simple terms, mode switching between the normal mode and slow mode is executed using the cks2~cks0 bits in the scc register while mode switching from the normal/slow modes to the sleep/idle modes is executed via the halt instruction. when an halt instruction is executed, whether the devices enter the idle mode or the sleep mode is determined by the condition of the fhiden and fsiden bits in the scc register. normal f sys =f h ~f h /64 f h on cpu run f sys on f sub on slow f sys =f sub f sub on cpu run f sys on f h on/off idle0 halt instruction executed cpu stop fhiden=0 fsiden=1 f h off f sub on idle1 halt instruction executed cpu stop fhiden=1 fsiden=1 f h on f sub on idle2 halt instruction executed cpu stop fhiden=1 fsiden=0 f h on f sub off sleep halt instruction executed cpu stop fhiden=0 fsiden=0 f h off f sub off
rev. 1.00 28 july 19, 2017 rev. 1.00 29 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu normal mode to slow mode switching when running in the normal mode, which uses the high speed system oscillator, and therefore consumes more power, the system clock can switch to run in the slow mode by set the cks2~cks0 bits to "111" in the scc register. this will then use the low speed system oscillator which will consume less power. users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. the slow mode is sourced from the lirc oscillator and therefore requires this oscillator to be stable before full mode switching occurs. normal mode slow mode cks2~cks0 = 111 sleep mode fhiden=0, fsiden=0 halt instruction is executed idle0 mode fhiden=0, fsiden=1 halt instruction is executed idle1 mode fhiden=1, fsiden=1 halt instruction is executed idle2 mode fhiden=1, fsiden=0 halt instruction is executed
rev. 1.00 30 july 19, 2017 rev. 1.00 31 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu slow mode to normal mode switching in slow mode the system clock is derived from f sub . when system clock is switched back to the normal mode from f sub , the cks2~cks0 bits should be set to "000" ~"110" and then the system clock will respectively be switched to f h ~ f h /64. however, if f h is not used in slow mode and thus switched off, it will take some time to re- oscillate and stabilise when switching to the normal mode from the slow mode. this is monitored using the hircf bit in the hircc register. the time duration required for the high speed system oscillator stabilization is specifed in the a.c. characteristics. normal mode slow mode cks2~cks0 = 000~110 sleep mode fhiden=0, fsiden=0 halt instruction is executed idle0 mode fhiden=0, fsiden=1 halt instruction is executed idle1 mode fhiden=1, fsiden=1 halt instruction is executed idle2 mode fhiden=1, fsiden=0 halt instruction is executed entering the sleep mode there is only one way for the device to enter the sleep mode and that is to execute the "halt" instruction in the application program with both the fhiden and fsiden bits in the scc register equal to "0". when this instruction is executed under the conditions described above, the following will occur: ? the system clock will be stopped and the application program will stop at the "halt" instruction. ? the data memory contents and registers will maintain their present condition. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the watchdog time-out fag, to, will be cleared. ? the wdt will be cleared and resume counting if the wdt function is enabled. if the wdt function is disabled, the wdt will be cleared and then stopped.
rev. 1.00 30 july 19, 2017 rev. 1.00 31 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu entering the idle0 mode there is only one way for the device to enter the idle0 mode and that is to execute the "halt" instruction in the application program with the fhiden bit in the scc register equal to "0" and the fsiden bit in the scc register equal to "1". when this instruction is executed under the conditions described above, the following will occur: ? the f h clock will be stopped and the application program will stop at the "halt" instruction, but the f sub clock will be on. ? the data memory contents and registers will maintain their present condition. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the watchdog time-out fag, to, will be cleared. ? the wdt will be cleared and resume counting if the wdt function is enabled. if the wdt function is disabled, the wdt will be cleared and then stopped. entering the idle1 mode there is only one way for the device to enter the idle1 mode and that is to execute the "halt" instruction in the application program with both the fhiden and fsiden bits in the scc register equal to "1". when this instruction is executed under the conditions described above, the following will occur: ? the f h and f sub clocks will be on but the application program will stop at the "halt" instruction. ? the data memory contents and registers will maintain their present condition. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the watchdog time-out fag, to, will be cleared. ? the wdt will be cleared and resume counting if the wdt function is enabled. if the wdt function is disabled, the wdt will be cleared and then stopped. entering the idle2 mode there is only one way for the device to enter the idle2 mode and that is to execute the "halt" instruction in the application program with the fhiden bit in the scc register equal to "1" and the fsiden bit in scc register equal to "0". when this instruction is executed under the conditions described above, the following will occur: ? the f h clock will be on but the f sub clock will be off and the application program will stop at the "halt" instruction. ? the data memory contents and registers will maintain their present condition. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the watchdog time-out fag, to, will be cleared. ? the wdt will be cleared and resume counting if the wdt function is enabled. if the wdt function is disabled, the wdt will be cleared and then stopped.
rev. 1.00 32 july 19, 2017 rev. 1.00 33 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu standby current considerations as the main reason for entering the sleep or idle mode is to keep the current consumption of the device to as low a value as possible, perhaps only in the order of several micro-amps except in the idle1 and idle2 mode, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. special attention must be made to the i/o pins on the device. all high-impedance input pins must be connected to either a fxed high or low level as any foating input pins could create internal oscillations and result in increased current consumption. these must either be setup as outputs or if setup as inputs must have pull-high resistors connected. care must also be taken with the loads, which are connected to i/o pins, which are setup as outputs. these should be placed in a condition in which minimum current is drawn or connec ted only to external circuits that do not draw current, such as other cmos inputs. also note that additional standby current will also be required if the lirc oscillator has enabled. in the idle1 and idle2 mode the high speed oscillator is on, if the peripheral function clock source is derived from the high speed oscillator, the additional standby current will also be perhaps in the order of several hundred micro-amps. wake-up to minimise power consumption the device can enter the sleep or any idle mode, where the cpu will be switched off. however, when the device is woken up again, it will take a considerable time for the original system oscillator to restart, stablise and allow normal operation to resume. after the system enters the sleep or idle mode, it can be woken up from one of various sources listed as follows: ? an external falling edge on port a ? a system interrupt ? a wdt overfow when the device executes the "halt" instruction, the pdf fag will be set to 1. the pdf fag will be cleared to 0 if the device experiences a system power-up or executes the clear watchdog timer instruction. if the system is woken up by a wdt overfow, a watchdog timer reset will be initiated and the to fag will be set to 1. the to fag is set if a wdt time-out occurs and causes a wake-up that only resets the program counter and stack pointer, other fags remain in their original status. each pin on port a can be setup using the pawu register to permit a negative transition on the pin to wake up the system. when a port a pin wake-up occurs, the program will resume execution at the instruction following the "halt" instruction. if the system is woken up by an interrupt, then two possible situations may occur. the frst is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the "halt" instruction. in this situation, the interrupt which woke up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is fnally enabled or when a stack level becomes free. the other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. if an interrupt request flag is set high before entering the sleep or idle mode, the wake-up function of the related interrupt will be disabled.
rev. 1.00 32 july 19, 2017 rev. 1.00 33 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu watchdog timer the watchdog timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. watchdog timer clock source the watchdog timer clock source is provided by the internal clock, f lirc , which is sourced from the lirc oscillator. the lirc internal oscillator has an approximate frequency of 32khz and this specifed internal clock period can vary with v dd , temperature and process variations. the watchdog timer source clock is then subdivided by a ratio of 2 8 to 2 18 to give longer timeouts, the actual value being chosen using the ws2~ws0 bits in the wdtc register. watchdog timer control register a sing le register, wdtc, controls the required timeout period as well as the enable/disable and reset mcu operation. this register control s the overall operation of the watchdog timer. ? wdtc register bit 7 6 5 4 3 2 1 0 name we4 we3 we2 we1 we0 ws2 ws1 ws0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 0 1 1 bit 7~3 we4~we0 : wdt function software control 10101: disable 01010: enable other values : reset mcu when these bits are changed to any other values due to environmental noise the microcontroller will be reset; this reset operation will be activated after a delay time, t sreset , and the wrf bit in the rstfc register will be set high. bit 2~0 ws2~ws0 : wdt time-out period selection 00 0b: 2 8 /f lirc 001b : 2 9 /f lirc 01 0b: 2 10 /f lirc 011b : 2 11 /f lirc (default) 10 0b: 2 12 /f lirc 101b : 2 13 /f lirc 11 0b: 2 14 /f lirc 111b : 2 15 /f lirc these three bits determine the division ratio of the watchdog timer source clock, which in turn determines the timeout period. ? rstfc register bit 7 6 5 4 3 2 1 0 name wrf r/w r/w por 0 bit 7~1 unimplemented, read as "0" bit 0 wrf : wdt control register software reset fag 0: not occurred 1: occurred this bit is set to 1 by the wdt control register software reset and cleared by the application program. note that this bit can only be cleared to 0 by the application program.
rev. 1.00 34 july 19, 2017 rev. 1.00 35 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu watchdog timer operation the watchdog timer operates by providing a device reset when its timer overfows. this means that in the application program and during normal operation the user has to strategically clear the watchdog timer before it overfows to prevent the watchdog timer from executing a reset. this is done using the clear watchdog instructions. if the program malfunctions for whatever reason, jumps to an unknown location, or enters an endless loop, these clear instructions will not be executed in the correct manner, in which case the watchdog timer will overfow and reset the device. t here are fve bits, we4~we0, in the wdtc register to offer additional enable/disable and reset control of the watchdog timer. the wdt function will be disabled when the we4~we0 bits are set to a value of 10101b. the wdt function will be enabled if the we4~we0 bits value is equal to 01010b. if the we4~we0 bits are set to any other values, other than 01010b and 10101b, it will reset the device after a delay time, t sreset . after power on these bits will have the value of 01010b. we4~we0 bits wdt function 10101b disable 01010b enable any other value reset mcu watchdog timer enable/disable control under normal program operation, a watchdog timer time-out will initialise a device reset and set the status bit to. however, if the system is in the sleep or idle mode, when a watchdog timer time-out occurs, the to bit in the status register will be set and only the program counter and stack pointer will be reset. three methods can be adopted to clear the contents of the watchdog timer. the frst is a wdt reset, which means a certain value except 01010b and 10101b written into the we4~we0 bit fled, the second is using the watchdog timer software clear instruction and the third is via a halt instruction. there is only one method of using software instruction to clear the watchdog timer. that is to use the single "clr wdt" instruction to clear the wdt. the maximum time out period is when the 2 18 division ratio is selected. as an example, with a 32khz lirc oscillator as its source clock, this will give a maximum watchdog period of around 8 seconds for the 2 18 division ratio, and a minimum timeout of 8ms for the 2 8 division ration. clr wdt instruction 8-stage divider wdt prescaler we4~we0 bits wdtc register reset mcu f lirc f lirc /2 8 8-to-1 mux clr ws2~ws0 wdt time-out (2 8 /f lirc ~ 2 18 /f lirc ) halt instruction lirc watchdog timer
rev. 1.00 34 july 19, 2017 rev. 1.00 35 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu reset and initialisation a reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. the most important reset condition is after power is frst applied to the microcontroller. in this case, internal circuitry will ensure that the microcontroller, after a short delay, will be in a well-defined state and ready to execute the frst program instruction. after this power-on reset, certain important internal registers will be set to defned states before the program commences. one of these registers is the program counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest program memory address. another type of reset is when the watchdog timer overflows and resets the microcontroller. all types of reset operations result in different register conditions being setup. reset functions there are several ways in which a microcontroller reset can occur, through events occurring internally. power-on reset the most fundamental and unavoidable reset is the one that occurs after power is frst applied to the microcontroller. as well as ensuring that the program memory begins execution from the frst memory address, a power-on reset also ensures that certain other registers are preset to known conditions. all the i/o port and port control registers will power up in a high condition ensuring that all pins will be frst set to inputs. v dd power-on reset sst time-out t rstd power-on reset timing chart watchdog time-out reset during normal operation the watchdog time-out reset during normal operations in the normal or slow mode is the same as a power on reset except that the watchdog time-out fag to will be set to "1". wdt time-out internal reset t rstd + t sst wdt time-out reset during normal operation timing chart watchdog time-out reset during sleep or idle mode the watchdog time-out reset during sleep or idle mode is a little different from other kinds of reset. most of the conditions remain unchanged except that the program counter and the stack pointer will be cleared to "0" and the to fag will be set to "1". refer to the a.c. characteristics for t sst details. wdt time-out internal reset t sst wdt time-out reset during sleep or idle timing chart
rev. 1.00 36 july 19, 2017 rev. 1.00 37 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu reset initial conditions the different types of reset described affect the reset fags in different ways. these fags, known as pdf and to are located in the status register and are controlled by various microcontroller operations, such as the sleep or idle mode function or watchdog timer. the reset flags are shown in the table: to pdf reset conditions 0 0 power-on reset 1 u wdt time-out reset during normal or slow mode operation 1 1 wdt time-out reset during idle or sleep mode operation note: "u" stands for unchanged the following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. item condition after reset program counter reset to zero interrupts all interrupts will be disabled wdt,time base clear after reset, wdt begins counting timer modules timer modules will be turned off input/output ports i/o ports will be setup as inputs stack pointer stack pointer will point to the top of the stack the different kinds of resets all affect the internal registers of the microcontroller in different ways. to ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. the following table describes how each type of reset affects each of the microcontroller internal registers. note that where more than one package type exists the table will refelect the situation for the larger package type. register power on reset wdt time-out (normal operation) wdt time-out (idle/sleep) program counter 000h 000h 000h mp0 1xxx xxxx 1xxx xxxx 1uuu uuuu mp1 1xxx xxxx 1xxx xxxx 1uuu uuuu acc xxxx xxxx uuuu uuuu uuuu uuuu pcl 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx uuuu uuuu uuuu uuuu tblh --xx xxxx --uu uuuu --uu uuuu tbhp ---- --xx ---- --uu ---- --uu status --00 xxxx --1u uuuu --11 uuuu rstfc ---- ---0 ---- ---u ---- ---u intc0 -000 0000 -000 0000 -uuu uuuu intc1 --00 --00 --00 --00 --uu --uu mfi0 --00 --00 --00 --00 --uu --uu mfi1 --00 --00 --00 --00 --uu --uu mfi2 --00 --00 --00 --00 --uu --uu pa 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 uuuu uuuu papu 0000 0000 0000 0000 uuuu uuuu pawu 0000 0000 0000 0000 uuuu uuuu wdtc 0101 0011 0101 0011 uuuu uuuu
rev. 1.00 36 july 19, 2017 rev. 1.00 37 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu register power on reset wdt time-out (normal operation) wdt time-out (idle/sleep) pscr ---- --00 ---- --00 ---- --uu tbc 0--- -000 0--- -000 u--- -uuu scc 000- --00 000- --00 uuu- --uu hircc ---- --01 ---- --01 ---- --uu pas0 0000 00-- 0000 00-- uuuu uu-- pas1 0000 0000 0000 0000 uuuu uuuu ifs ---- ---0 ---- ---0 ---- ---u ctm0c0 0000 0000 0000 0000 uuuu uuuu ctm0c1 0000 0000 0000 0000 uuuu uuuu ctm0dl 0000 0000 0000 0000 uuuu uuuu ctm0dh ---- --00 ---- --00 ---- --uu ctm0al 0000 0000 0000 0000 uuuu uuuu ctm0ah ---- --00 ---- --00 ---- --uu ctm1c0 0000 0000 0000 0000 uuuu uuuu ctm1c1 0000 0000 0000 0000 uuuu uuuu ctm1dl 0000 0000 0000 0000 uuuu uuuu ctm1dh ---- --00 ---- --00 ---- --uu ctm1al 0000 0000 0000 0000 uuuu uuuu ctm1ah ---- --00 ---- --00 ---- --uu ctm2c0 0000 0000 0000 0000 uuuu uuuu ctm2c1 0000 0000 0000 0000 uuuu uuuu ctm2dl 0000 0000 0000 0000 uuuu uuuu ctm2dh ---- --00 ---- --00 ---- --uu ctm2al 0000 0000 0000 0000 uuuu uuuu ctm2ah ---- --00 ---- --00 ---- --uu cascon -100 0000 -100 0000 -uuu uuuu caspre ---- -000 ---- -000 ---- -uuu casth ---0 0111 ---0 0111 ---u uuuu d0cnt ---0 0100 ---0 0100 ---u uuuu d1cnt ---0 1010 ---0 1010 ---u uuuu pcnt 0001 1000 0001 1000 uuuu uuuu rcnt 1000 0000 1000 0000 uuuu uuuu casd0 0000 0000 0000 0000 uuuu uuuu casd1 0000 0000 0000 0000 uuuu uuuu casd2 0000 0000 0000 0000 uuuu uuuu intcon 0000 0000 0000 0000 uuuu uuuu ccs 0010 --00 0010 --00 uuuu --uu note: "u" stands for unchanged "x" stands for unknown "-" stands for unimplemented
rev. 1.00 38 july 19, 2017 rev. 1.00 39 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu input/output ports holtek microcontrollers offer considerable fexibility on their i/o ports. with the input or output designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an i/o structure to meet the needs of a wide range of application possibilities. the device provides bidirectional input/output lines labeled with port name pa. these i/o ports are mapped to the ram data memory with specific addresses as shown in the special purpose data memory table. all of these i/o ports can be used for input and output operations. for input operation, these ports are non-latching, which means the inputs must be ready at the t2 rising edge of instruction "mov a, [m]", where m denotes the port address. for output operation, all the data is latched and remains unchanged until the output latch is rewritten. register name bit 7 6 5 4 3 2 1 0 pa pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 pac pac7 pac6 pac5 pac4 pac3 pac2 pac1 pac0 papu papu7 papu6 papu5 papu4 papu3 papu2 papu1 papu0 pawu pawu7 pawu6 pawu5 pawu4 pawu3 pawu2 pawu1 pawu0 i/o logic function register list pull-high resistors many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. to eliminate the need for these external resistors, all i/o pins, when configured as an input have the capability of being connected to an internal pull-high resistor. these pull-high resistors are selected using the relevant pull-high control registers papu, and are implemented using weak pmos transistors. note that the pull-high resistor can be controlled by the relevant pull-high control registers only when the pin-shared functional pin is selected as a input or nmos output. otherwise, the pull-high resistors cannot be enabled. ? papu register bit 7 6 5 4 3 2 1 0 name papu7 papu6 papu5 papu4 papu3 papu2 papu1 papu0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 papu7~papu0 : port a bit 7 ~ bit 0 pull-high control 0: disable 1: enable port a wake-up the halt instruction forces the microcontroller into the sleep or idle mode which preserves power, a feature that is important for battery and other low-power applications. various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the port a pins from high to low. this function is especially suitable for applications that can be woken up via external switches. each pin on port a can be selected individually to have this wake-up feature using the pawu register. note that the wake-up function can be controlled by the wake-up control registers only when the pin-shared functional pin is selected as general purpose input/output and the mcu enters the power down mode.
rev. 1.00 38 july 19, 2017 rev. 1.00 39 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu ? pawu register bit 7 6 5 4 3 2 1 0 name pawu7 pawu6 pawu5 pawu4 pawu3 pawu2 pawu1 pawu0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 pawu7~pawu0 : port a bit 7 ~ bit 0 wake-up control 0: disable 1: enable i/o port control registers each i/o port has its own control register known as pac, to control the input/output confguration. with this control register, each cmos output or input can be reconfigured dynamically under software control. each pin of the i/o ports is directly mapped to a bit in its associated port control register. for the i/o pin to function as an input, the corresponding bit of the control register must be written as a "1". this will then allow the logic state of the input pin to be directly read by instructions. when the corresponding bit of the control register is written as a "0", the i/o pin will be setup as a cmos output. if the pin is currently setup as an output, instructions can still be used to read the output register. however, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. ? pac register bit 7 6 5 4 3 2 1 0 name pac7 pac6 pac5 pac4 pac3 pac2 pac1 pac0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 bit 7~0 pac7~pac0 : port a bit 7 ~ bit 0 input/output control 0: output 1: input pin-shared functions the fexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these diffculties can be overcome. for these pins, the desired function of the multi-function i/o pins is selected by a series of registers via the application program control. pin-shared function selection registers the limited number of supplied pins in a package can impose restrictions on the amount of functions a certain device can contain. however by allowing the same pins to share several different functions and providing a mea ns of function selection, a wide range of different functions can be incorporated into even relatively small package sizes. the device includes port "a" pin shared function selection registers, labeled as pasn, and input function selection register, labeled as ifs, which can select the desired functions of the multi-function pin-shared pins. when the pin-shared input function is selected to be used, the corresponding input and output functions selection should be properly managed. for example, if the cascading transceiver interface is used, the corresponding pin-shared function should be confgured as the cascading transceiver interface function by confguring the pas0 register and the cascading transceiver interface signal input pin should be properly selected using the ifs register. if the external interrupt function is selected to be used, the relevant pin-shared function should be selected as an i/o function and the interrupt input signal active edge should be selected.
rev. 1.00 40 july 19, 2017 rev. 1.00 41 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu the most important point to note is to make sure that the desired pin-shared function is properly selected and also deselected. for most pin-shared functions, to select the desired pin-shared function, the pin-shared function should frst be correctly selected using the corresponding pin-shared control register. after that the corresponding peripheral functional setting should be confgured and then the peripheral function can be enabled. however, a special point must be noted for some digital input pins, such as casdi, etc, which share the same pin-shared control confguration with their corresponding general purpose i/o functions when setting the relevant pin-shared control bit felds. to select these pin functions, in addition to the necessary pin-shared control and peripheral functional setup aforementioned, they must also be setup as an input by setting the corresponding bit in the i/o port control register. to correctly deselect the pin-shared function, the peripheral function should first be disabled and then the corresponding pin-shared function control register can be modifed to select other pin-shared functions. register name bit 7 6 5 4 3 2 1 0 pas0 pas07 pas06 pas05 pas04 pas03 pas02 pas1 pas17 pas16 pas15 pas14 pas13 pas12 pas11 pas10 ifs ifs0 pin-shared function selection registers list ? pas0 register bit 7 6 5 4 3 2 1 0 name pas07 pas06 pas05 pas04 pas03 pas02 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 pas07~pas06 : pa3 pin-shared function selection 00: pa3 01: pa3 10: pa3 11: casdi bit 5~4 pas05~pas04 : pa2 pin-shared function selection 00: pa2 01: pa2 10: pa2 11: casdi bit 3~2 pas03~pas02 : pa1 pin-shared function selection 00: pa1 01: pa1 10: pa1 11: casdo bit 1~0 unimplemented, read as "0" ? pas1 register bit 7 6 5 4 3 2 1 0 name pas17 pas16 pas15 pas14 pas13 pas12 pas11 pas10 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 pas17~pas16 : pa7 pin-shared function selection 00: pa7 01: pa7 10: pa7 11: cco2
rev. 1.00 40 july 19, 2017 rev. 1.00 41 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu bit 5~4 pas15~pas14 : pa6 pin-shared function selection 00: pa6 01: pa6 10: pa6 11: cco1 bit 3~2 pas13~pas12 : pa5 pin-shared function selection 00: pa5 01: pa5 10: pa5 11: cco0 bit 1~0 pas11~pas10 : pa4 pin-shared function selection 00: pa4 01: pa4 10: pa4 11: casdo ? ifs register bit 7 6 5 4 3 2 1 0 name ifs0 r/w r/w por 0 bit 7~1 unimplemented, read as "0" bit 0 ifs0 : cascading transceiver interface source selection 0: pa3 1: pa2 i/o pin structures the accompanying diagram illustrates the internal structure of the i/o logic function. as the exact logical construction of the i/o pin will differ from this drawing, it is supplied as a guide only to assist with the functional understanding of the i/o logic function. the wide range of pin-shared structures does not permit all types to be shown. m u x vdd control bit data bit data bus write control register chip reset read control register read data register write data register system wake-up wake-up select i/o pin weak pull-up pull-high register select q d ck q d ck q q s s logic function input/output structure
rev. 1.00 42 july 19, 2017 rev. 1.00 43 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu programming considerations within the user program, one of the frst things to consider is port initialisation. after a reset, all of the i/o data and port control registers will be set high. this means that all i/o pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high selections have been chosen. if the port control register, pac, are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data register, pa, are frst programmed. selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the "set [m].i" and "clr [m].i" instructions. note that when using these bit control instructions, a read-modify-write operation takes place. the microcontroller must frst read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. port a has the additional capability of providing wake-up functions. when the device is in the sleep or idle mode, various methods are available to wake the device up. one of these is a high to low transition of any of the port a pins. single or multiple pins on port a can be setup to have this function.
rev. 1.00 42 july 19, 2017 rev. 1.00 43 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu timer modules C tm one of the most fundamental functions in any microcontroller device is the ability to control and measure time. to implement time related functions this device includes several timer modules, abbreviated to the name tm. the tms are multi-purpose timing units and serve to provide operations such as timer/counter, compare match output as well as being the functional unit for the generation of pwm signals. each of the tms has two individual interrupts. the addition of input and output pins for each tm ensures that users are provided with timing units with a wide and fexible range of features. the general features of the compact type tm are described here with more detailed information provided in the compact type tm section. introduction the device contains three compact type tms having a reference name of c tm0 , c tm1 and ctm2 . the common features to the compact tms will be described in this section and the detailed operation will be described in the corresponding sections. the main features of the c tm are summarised in the accompanying table. function ctm timer/counter input capture compare match output pwm channels 1 single pulse output pwm alignment edge pwm adjustment period & duty duty or period tm function summary tm operation the compact type tms offer a diverse range of functions, from simple timing operations to pwm signal generation. the key to understanding how the tm operates is to see it in terms of a free running counter whose value is then compared with the value of pre-programmed internal comparators. when the free running counter has the same value as the pre-programmed comparator, known as a compare match situation, a tm interrupt signal will be generated which can clear the counter and perhaps also change the condition of the tm output pin. the internal tm counter is driven by a user selectable clock source, which can be an internal clock. tm clock source the clock source which drives the main counter in the tm can originate from various sources. the selection of the required clock source is implemented using the ctnck2~ctnck0 bits in the ctmn control registers. the clock source can be a ratio of the system clock f sys or the internal high clock f h , the f sub clock source. tm interrupts the compact type tms each have two internal interrupts, one for each of the internal comparator a or comparator p, which generate a tm interrupt when a compare match condition occurs. when a tm interrupt is generated it can be used to clear the counter and also to change the state of the tm output pin.
rev. 1.00 44 july 19, 2017 rev. 1.00 45 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu tm external pins the tms each have two output pins, ctpn and ctpnb. the ctpnb is the inverted signal of the ctpn output. when the tm is in the compare match output mode, these pins can be controlled by the tm to switch to a high or low level or to toggle when a compare match situation occurs. the external ctpn and ctpnb output pins are also the pins where the tm generates the pwm output waveform. ctm0 outpu t ctm1 output ctm2 output ctp0, ctp0b ctp1, ctp1b ctp1, ctp1b tm external pins programming considerations the tm counter registers, the capture/compare ccra register, being 10-bit, has a low and high byte structure. the high byte can be directly accessed, but as the low byte can only be accessed via an internal 8-bit buffer, reading or writing to this register pair must be carried out in a specifc way. the important point to note is that data transfer to and from the 8-bit buffer and its related low byte only takes place when a write or read operation to its corresponding high byte is executed. as the ccra register is implemented in the way shown in the following diagram and accessing these registers is carried out in a specifc way described above, it is recommended to use the "mov" instruction to access the ccra low byte register, named ctmnal, using the following access procedures. accessing the ccra low byte register without following these access procedures will result in unpredictable values. data bus 8-bit buffer ctmndh ctmndl ctmnah ctmnal ctmn counter register (read only) ctmn ccra register (read/write) the following steps show the read and write procedures: ? writing data to ccra ? step 1. write data to low byte ctmnal C note that here data is only written to the 8-bit buffer. ? step 2. write data to high byte ctmnah C here data is written directly to the high byte registers and simultaneously data is latched from the 8-bit buffer to the low byte registers. ? reading data from the counter registers and or ccra ? step 1. read data from the high byte ctmndh or ctmnah C here data is read directly from the high byte registers and simultaneously data is latched from the low byte register into the 8-bit buffer. ? step 2. read data from the low byte ctmndl or ctmnal C this step reads data from the 8-bit buffer.
rev. 1.00 44 july 19, 2017 rev. 1.00 45 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu compact type tm C ctm although the simplest form of the three tm types, the compact tm type still contains three operating modes, which are compare match output, timer/event counter and pwm output modes. the compact tm can drive two external output pins. f sys f sys /4 f h /64 f h /16 f sub 000 001 010 011 100 101 ctnck2~ctnck0 10-bit count-up counter 3-bit comparator p ccrp b7~b9 b0~b9 10-bit comparator a ctnon ctnpau comparator a match comparator p match counter clear 0 1 output control polarity control ctpn ctnoc ctnm1, ctnm0 ctnio1, ctnio0 ctmnaf interrupt ctmnpf interrupt ctnpol ccra ctncclr f sub ctpnb note: the ctpn pin can be source for rgbn pwm input. more information is provided in the constant current led driver section. compact type tm block diagram (n=0~2) compact tm operation the compact type tm core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. there are also two internal comparators with the names, comparator a and comparator p. these comparators will compare the value in the counter with ccrp and ccra registers. the ccrp is three bits wide whose value is compared with the highest three bits in the counter while the ccra is the ten bits and therefore compares with all counter bits. the only way of changing the value of the 10-bit counter using the application program, is to clear the counter by changing the ctnon bit from low to high. the counter will also be cleared automatically by a counter overfow or a compare match with one of its associated comparators. when these conditions occur, a ctmn interrupt signal will also usually be generated. the compact type tm can operate in a number of different operational modes, can be driven by different clock sources and can also control two output pins. all operating setup conditions are selected using relevant internal registers. compact type tm register description overall operation of the compact type tm is controlled using a series of registers. a read only register pair exists to store the internal counter 10-bit value, while a read/write register pair exists to store the internal 10-bit ccra value. the remaining two registers are control registers which setup the different operating and control modes as well as the three ccrp bits. register name bit 7 6 5 4 3 2 1 0 ctmnc0 ctnpau ctnck2 ctnck1 ctnck0 ctnon ctnrp2 ctnrp1 ctnrp0 ctmnc 1 ctnm1 ctnm0 ctnio1 ctnio0 ctnoc ctnpol ctndpx ctncclr ctmndl d7 d6 d5 d4 d3 d2 d1 d0 ctmndh d9 d8 ctmnal d7 d6 d5 d4 d3 d2 d1 d0 ctmnah d9 d8 10-bit compact tm register list
rev. 1.00 46 july 19, 2017 rev. 1.00 47 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu ? ctmnc0 register bit 7 6 5 4 3 2 1 0 name ctnpau ctnck2 ctnck1 ctnck0 ctnon ctnrp2 ctnrp1 ctnrp0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 ctnpau : ctmn counter pause control 0: run 1: pause the counter can be paused by setting this bit high. clearing the bit to zero restores normal counter operation. when in a pause condition the ctm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 ctnck2~ctnck0 : select ctmn counter clock 000: f sys /4 001: f sys 010: f h /16 011: f h /64 100: f sub 101: f sub 110: undefned, cannot be selected 111: undefned, cannot be selected these three bits are used to select the clock source for the ctm. the clock source f sys is the system clock, while f h and f sub are other internal clocks, the details of which can be found in the oscillator section. bit 3 ctnon : ctmn counter on/off control 0: off 1: on this bit controls the overall on/off function of the ctm. setting the bit high enables the counter to run, clearing the bit disables the ctm. clearing this bit to zero will stop the counter from counting and turn off the ctm which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. if the ctm is in the compare match output mode or the pwm output mode then the ctm output pin will be reset to its initial condition, as specifed by the ctnoc bit, when the ctnon bit changes from low to high. bit 2~0 ctnrp2~ctnrp0 : ctmn ccrp 3-bit register, compared with the ctmn counter bit 9~bit 7 comparator p match period 000: 1024 ctm n clocks 001: 128 ctm n clocks 010: 256 ctm n clocks 011: 384 ctm n clocks 100: 512 ctm n clocks 101: 640 ctm n clocks 110: 768 ctm n clocks 111: 896 ctm n clocks these three bits are used to setup the value on the internal ccrp 3-bit register, which are then compared with the internal counter's highest three bits. the result of this comparison can be selected to clear the internal counter if the ctncclr bit is set to zero. setting the ctncclr bit to zero ensures that a compare match with the ccrp values will reset the internal counter. as the ccrp bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value.
rev. 1.00 46 july 19, 2017 rev. 1.00 47 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu ? ctmnc1 register bit 7 6 5 4 3 2 1 0 name ctnm1 ctnm0 ctnio1 ctnio0 ctnoc ctnpol ctndpx ctncclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 ctnm1~ctnm0 : select ctmn operating mode 00: compare match output mode 01: undefned 10: pwm output mode 11: timer/counter mode these bits setup the required operating mode for the ctm. to ensure reliable operation the ctm should be switched off before any changes are made to the ctnm1 and ctnm0 bits. in the timer/counter mode, the ctm output pin state is undefned. bit 5~4 ctnio1~ctnio0 : select ctpn output function compare match output mode 00: no change 01: output low 10: output high 11: toggle output pwm output mode 00: pwm output inactive state 01: pwm output active state 10: pwm o utput 11: undefned timer/counter mode unused these two bits are used to determine how the ctm output pin changes state when a certain condition is reached. the function that these bits select depends upon in which mode the ctm is running. in the compare match output mode, the ctnio1 and ctnio0 bits determine how the ctm output pin changes state when a compare match occurs from the comparator a. the ctm output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the ctm output pin should be setup using the ctnoc bit in the ctmnc1 register. note that the output level requested by the ctnio1 and ctnio0 bits must be different from the initial value setup using the ctnoc bit otherwise no change will occur on the ctm output pin when a compare match occurs. after the ctm output pin changes state it can be reset to its initial level by changing the level of the ctnon bit from low to high. in the pwm output mode, the ctnio1 and ctnio0 bits determine how the ctm output pin changes state when a certain compare match condition occurs. the pwm output function is modifed by changing these two bits. it is necessary to only change the values of the ctnio1 and ctnio0 bits only after the ctmn has been switched off. unpredictable pwm outputs will occur if the ctnio1 and ctnio0 bits are changed when the ctm is running.
rev. 1.00 48 july 19, 2017 rev. 1.00 49 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu bit 3 ctnoc : ctpn output control bit compare match output mode 0: initial low 1: initial high pwm output mode 0: active low 1: active high this is the output control bit for the ctm output pin. its operation depends upon whether ctm is being used in the compare match output mode or in the pwm output mode. it has no effect if the ctm is in the timer/counter mode. in the compare match output mode it determines the logic level of the ctm output pin before a compare match occurs. in the pwm output mode it determines if the pwm signal is active high or active low. bit 2 ctnpol : ctpn output polarity control 0: non-invert 1: invert this bit controls the polarity of the ctpn output pin. when the bit is set high the ctm output pin will be inverted and not inverted when the bit is zero. it has no effect if the ctm is in the timer/counter mode. bit 1 ctndpx : ctmn pwm period/duty control 0: ccrp C period, ccra C duty 1: ccrp C duty; ccra C period this bit, determines which of the ccra and ccrp registers are used for period and duty control of the pwm waveform. bit 0 ctncclr : select ctmn counter clear condition 0: ctm n comparatror p match 1: ctm n comparatror a match this bit is used to select the method which clears the counter. remember that the compact tm contains two comparators, comparator a and comparator p, either of which can be selected to clear the internal counter. with the ctncclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low, the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow. a counter overfow clearing method can only be implemented if the ccrp bits are all cleared to zero. the ctncclr bit is not used in the pwm output mode. ? ctmndl register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 d7~d0 : ctmncounter low byte register bit 7 ~ bit 0 ctmn 10-bit counter bit 7 ~ bit 0 ? ctmndh register bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r r por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 d9~d8 : ctmn counter high byte register bit 1 ~ bit 0 ctmn 10-bit counter bit 9 ~ bit 8
rev. 1.00 48 july 19, 2017 rev. 1.00 49 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu ? ctmnal register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 d7~d0 : ctmn ccra low byte register bit 7 ~ bit 0 ctmn 10-bit ccra bit 7 ~ bit 0 ? ctmnah register bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 d9~d8 : ctmn ccra high byte register bit 1 ~ bit 0 ctmn 10-bit ccra bit 9 ~ bit 8 compact type tm operating modes the compact type tm can operate in one of three operating modes, compare match output mode, pwm output mode or timer/counter mode. the operating mode is selected using the ctnm1 and ctnm0 bits in the ctmnc1 register. compare match output mode to select this mode, bits ctnm1 and ctnm0 in the ctmnc1 register, should be set to 00 respectively. in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow, a compare match from comparator a and a compare match from comparator p. when the ctncclr bit is low, there are two ways in which the counter can be cleared. one is when a compare match occurs from comparator p, the other is when the ccrp bits are all zero which allows the counter to overfow. here both ctmnaf and ctmnpf interrupt request fags for the comparator a and comparator p respectively, will both be generated. if the ctncclr bit in the ctmnc1 register is high then the counter will be cleared when a compare match occurs from comparator a. however, here only the ctmnaf interrupt request fag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when ctncclr is high no ctmnpf interrupt request fag will be generated. if the ccra bits are all zero, the counter will overfow when it reaches its maximum 10-bit, 3ff hex, value, however here the ctmnaf interrupt request fag will not be generated. as the name of the mode suggests, after a comparison is made, the ctm output pin will change state. the ctm output pin condition however only changes state when an ctmnaf interrupt request fag is generated after a compare match occurs from comparator a. the ctmnpf interrupt request fag, generated from a compare match occurs from comparator p, will have no effect on the ctm output pin. the way in which the ctm output pin changes state are determined by the condition of the ctnio1 and ctnio0 bits in the ctmnc1 register. the ctm output pin can be selected using the ctnio1 and ctnio0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from comparator a. the initial condition of the ctm output pin, which is setup after the ctnon bit changes from low to high, is setup using the ctnoc bit. note that if the ctnio1 and ctnio0 bits are zero then no pin change will take place.
rev. 1.00 50 july 19, 2017 rev. 1.00 51 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu counter value 0x3ff ccrp ccra ctnon ctnpau ctnpol ccrp int. flag ctmnpf ccra int. flag ctmnaf ctmn o/p pin time ccrp=0 ccrp > 0 counter overflow ccrp > 0 counter cleared by ccrp value pause resume stop counter restart ctncclr = 0; ctnm [1:0] = 00 output pin set to initial level low if ctnoc=0 output toggle with ctmnaf flag note ctnio [1:0] = 10 active high output select here ctnio [1:0] = 11 toggle output select output not affected by ctmnaf flag. remains high until reset by ctnon bit output pin reset to initial value output controlled by other pin-shared function output inverts when ctnpol is high compare match output mode C ctncclr=0(n=0~2) note: 1. with ctncclr = 0, a comparator p match will clear the counter 2. the ctm output pin controlled only by the ctmnaf fag 3. the output pin reset to initial state by a ctnon bit rising edge
rev. 1.00 50 july 19, 2017 rev. 1.00 51 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu counter value 0x3ff ccrp ccra ctnon ctnpau ctnpol ctmn o/p pin time ccra=0 ccra = 0 counter overflow ccra > 0 counter cleared by ccra value pause resume stop counter restart output pin set to initial level low if ctnoc=0 output toggle with ctmnaf flag note ctnio [1:0] = 10 active high output select here ctnio [1:0] = 11 toggle output select output not affected by ctmnaf flag. remains high until reset by ctnon bit output pin reset to initial value output controlled by other pin-shared function output inverts when ctnpol is high ctmnpf not generated no ctmnaf flag generated on ccra overflow output does not change ctncclr = 1; ctnm [1:0] = 00 ccra int. flag ctmnaf ccrp int. flag ctmnpf compare match output mode C ctncclr=1(n=0~2) note: 1. with ctncclr = 1, a comparator a match will clear the counter 2. the ctm output pin controlled only by the ctmnaf fag 3. the output pin reset to initial state by a ctnon bit rising edge 4. the ctmnpf fags is not generated when ctncclr = 1
rev. 1.00 52 july 19, 2017 rev. 1.00 53 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu timer/counter mode to select this mode, bits ctnm1 and ctnm0 in the ctmnc1 register should be set to 11 respectively. the timer/counter mode operates in an identical way to the compare match output mode generating the same interrupt flags. the exception is that in the timer/counter mode the ctm output pin is not used. therefore the above description and timing diagrams for the compare match output mode can be used to understand its function. pwm output mode to select this mode, bits ctnm1 and ctnm0 in the ctmnc1 register should be set to 10 respectively. the pwm function within the ctm is useful for applications which require functions such as motor control, heating control, illumination control etc. by providing a signal of fixed frequency but of varying duty cycle on the ctm output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform is extremely fexible. in the pwm output mode, the ctncclr bit has no effect on the pwm operation. both of the ccra and ccrp registers are used to generate the pwm waveform, one register is used to clear the internal counter and thus control the pwm waveform frequency, while the other one is used to control the duty cycle. which register is used to control either frequency or duty cycle is determined using the ctndpx bit in the ctmnc1 register. the pwm waveform frequency and duty cycle can therefore be controlled by the values in the ccra and ccrp registers. an interrupt fag, one for each of the ccra and ccrp, will be generated when a compare match occurs from either comparator a or comparator p. the ctnoc bit in the ctmnc1 register is used to select the required polarity of the pwm waveform while the two ctnio1 and ctnio0 bits are used to enable the pwm output or to force the ctm output pin to a fxed high or low level. the ctnpol bit is used to reverse the polarity of the pwm output waveform. ctm, pwm output mode, edge-aligned mode, ctndpx=0 ccrp 001b 010b 011b 100b 101b 110b 111b 000b period 128 256 384 512 640 768 896 1024 duty ccra if f sys = 8mhz, ctm clock source is f sys /4, ccrp = 100b, ccra =128, the ctm pwm output frequency = (f sys /4) / 512 = f sys /2048 = 3.9063khz, duty = 128/512 = 25%. if the duty value defned by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%. ctm, pwm output mode, edge-aligned mode, ctndpx=1 ccrp 001b 010b 011b 100b 101b 110b 111b 000b period ccra duty 128 256 384 512 640 768 896 1024 the pwm output period is determined by the ccra register value together with the ctm clock while the pwm duty cycle is defned by the ccrp register value.
rev. 1.00 52 july 19, 2017 rev. 1.00 53 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu counter value ccrp ccra ctnon ctnpau ctnpol ctmn o/p pin (ctnoc=1) time counter cleared by ccrp pause resume counter stop if ctnon bit low counter reset when ctnon returns high pwm duty cycle set by ccra pwm resumes operation output controlled by other pin-shared function output inverts when ctnpol = 1 pwm period set by ccrp ctmn o/p pin (ctnoc=0) ccra int. flag ctmnaf ccrp int. flag ctmnpf ctndpx = 0; ctnm [1:0] = 10 pwm output mode C ctndpx=0(n=0~2) note: 1. here ctndpx = 0 - counter cleared by ccrp 2. a counter clear sets the pwm period 3. the internal pwm function continues running even when ctnio[1:0] = 00 or 01 4. the ctncclr bit has no infuence on pwm operation
rev. 1.00 54 july 19, 2017 rev. 1.00 55 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu counter value ccrp ccra ctnon ctnpau ctnpol ccrp int. flag ctmnpf ccra int. flag ctmnaf ctmn o/p pin (ctnoc=1) time counter cleared by ccra pause resume counter stop if ctnon bit low counter reset when ctnon returns high pwm duty cycle set by ccrp pwm resumes operation output controlled by other pin-shared function output inverts when ctnpol = 1 pwm period set by ccra ctmn o/p pin (ctnoc=0) ctndpx = 1; ctnm [1:0] = 10 pwm output mode C ctndpx=1(n=0~2) note: 1. here ctndpx = 1 - counter cleared by ccra 2. a counter clear sets the pwm period 3. the internal pwm function continues even when ctnio[1:0] = 00 or 01 4. the ctncclr bit has no infuence on pwm operation
rev. 1.00 54 july 19, 2017 rev. 1.00 55 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu cascading transceiver interface cascade function is a feature of the led tape light. it can be issue from a master mcu, and transfer pwm data for rgb color led by single line cascading transceiver interface. the transfer rate is as soon as possible to make rgb led change color smoothly. it is noted that when cascading transceiver is the master device, the tx function is active. single line cascading transceiver interface is one-way transmission interface which contains an input casdi pin and an output casdo pin. when the rx circuit has received full 24 bits data, the transceiver will bypass the path to next device, and the next device will continue to read the following 24 bits data. the interception of 24 bits data in this sequence, which is called cascade function. casdi casdo casd1[7:0] r/w casd2[7:0] r/w casd0[7:0] r/w noise filter 1 0 8-bit shift register full24 empty24 casmod casmod caspre tx circuit d0cnt (5-bit) pcnt (8-bit) f cas1 f cas1 f cas2 = f cas1 /16 casres rx circuit casth (5-bit) passen trgtx f cas2 rcnt (8-bit) biterr casrxen caspre[2:0] f cas1 d1cnt (5-bit) f cas1 pcnten f cas1 biterr casmod casen f casclki note: the cascade clock f casclki is sourced from the system clock f sys. cascading transceiver interface block diagram casd2 casd1 casd0 first bit for transmission bit 7, bit 6 bit 0 bit 7, bit 6 bit 0 bit 7, bit 6 bit 0 24 bits data (one word) = casd2(8-bit)+casd1(8-bit)+casd0(8-bit) logic 0 data t tx_d0h t bit t tx_d0h = logic 0 high level count t bit = bit time period t tx_d0l = logic 0 low level count = t bit -t tx_d0h hang time t reset transceiver reset logic 1 data t reset = reset time count t tx_d1h t bit t tx_d0l t tx_d1l t tx_d1h = logic 1 high level count t tx_d1l = logic 1 low level count = t bit -t tx_d1h single line cascading transceiver interface data sequence
rev. 1.00 56 july 19, 2017 rev. 1.00 57 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu cascading transceiver interface register description overall operation of the cascading transceiver interface is controlled using a series of registers. the cascon and intcon registers are used for various cascading transceiver rx and tx function controls and interrupt control. the caspre register is used to select cascading transceiver clock. the casth register is used to specify the cascading transceiver rx function input data judgment threshold value. the d0cnt and d1cnt registers are used to control the cascading transceiver tx function logic 0 and logic 1 output data. the pcnt and rcnt registers are used to control the cascading transceiver data bit time period and reset time period. register name bit 7 6 5 4 3 2 1 0 cascon pcnten casrxen d4 trgtx passen casmod casen caspre caspre2 caspre1 caspre0 casth ths4 ths3 ths2 ths1 ths0 d0cnt lcnt4 lcnt3 lcnt2 lcnt1 lcnt0 d1cnt hcnt4 hcnt3 hcnt2 hcnt1 hcnt0 pcnt ps7 ps6 ps5 ps4 ps3 ps2 ps1 ps0 rcnt rs7 rs6 rs5 rs4 rs3 rs2 rs1 rs0 casd0 d7 d6 d5 d4 d3 d2 d1 d0 casd1 d7 d6 d5 d4 d3 d2 d1 d0 casd2 d7 d6 d5 d4 d3 d2 d1 d0 intcon biterr casres empty24 full24 berinten resinten eptinten fulinten cascading transceiver interface register list ? cascon register bit 7 6 5 4 3 2 1 0 name pcnten casrxen d4 trgtx passen casmod casen r/w r/w r/w r/w r/w r/w r/w r/w por 1 0 0 0 0 0 0 bit 7 unimplemented, read as "0" bit 6 pcnten : rx/tx transfer bit time counter control 0: disable 1: enable this bit is used to count the rx or tx data transfer bit time period. when the pcnten bit is cleared to 0, the bit time counter pcnt function will be disabled in the rx mode. it means that the bit time will not be checked and then the biterr fag will always be 0. for the tx mode the pcnt is always enabled and the pcnten bit has no effect on the pcnt function. when the pcnten bit is set to 1, the bit time counter pcnt function will be enabled. for the tx function the bit time counter is used to defne the transmit bit time. for the rx function the bit time counter is used to defne the maximum bit time. if the bit time counter underfows and no second rising edge appears on the casdi line, the biterr fag will be set to 1.
rev. 1.00 56 july 19, 2017 rev. 1.00 57 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu bit 5 casrxen : cascading transceiver rx function enable control 0: disable 1: enable this bit is used to control the cascading transceiver rx function. when this bit is set to 1, the cascading transceiver rx function will be enabled. this bit will automatically be cleared to 0 when the rx shift register full flag, full24, is set high. then it will automatically be set to 1 again when the cascading transceiver reset flag, casres, is set high. when this bit is set to 0, the cascading transceiver rx function will be disabled. however, the cascading transceiver reset signal can still be decoded and recognized as the rx function is disabled. note that the passen bit will automatically be cleared to 0 by hardware when the casrxen bit is set to 1 by hardware and vice versa. bit 4 d4 : reserved bit, should be fxed at "0". bit 3 trgtx : cascading transceiver tx output buffer trigger control 0: no action or data is transmitted completely 1: tx buffer output is triggered and data is transmitting continuously this bit can only be written into with a value of "1" when the casen bit is high. the trgtx bit will be cleared to 0 by hardware when the tx shift register empty fag, empty24, is set high. it will also be cleared to 0 when the casen bit is set low. note that the empty 24 bit will be cleared to 0 by hardware when the trgtx bit is set high by software regardless of the transceiver operation modes. setting the trgtx bit in the rx mode will have no operation. bit 2 passen : cascading transceiver input signal bypass rx circuit enable control 0: disable C not bypass the rx circuit 1: enable C bypass the rx circuit this bit controls the cascading transceiver input signal bypass function. it will automatically be set and cleared by hardware. when the casrxen bit is set to 1 by hardware to enable the cascading transceiver rx function, the passen bit will automatically be set to 0 by hardware and the cascading transceiver input signal will be decoded by the rx circuit. when the casrxen bit is cleared to 0 by hardware to disable the cascading transceiver rx function, the passen bit will automatically be set to 1 by hardware. at the same time the cascading transceiver input signal will bypass the rx circuit and directly be connected to the casdo line. bit 1 casmod : cascading transceiver tx or rx mode selection 0: rx mode 1: tx mode this bit can only be modified when the casen bit is set low. the cascading transceiver operating mode should frst be selected followed by setting the casen bit high. bit 0 casen : cascading transceiver enable control 0: disable 1: enable this bit is used to enable or disable the cascading transceiver function. when it is cleared to 0 to disable the cascading transceiver function, only the internal control circuit and corresponding read-only fags in the intcon register together with the trgtx bit will be reset. other registers contents will be kept unchanged. note that in the rx mode the contents of the casd0~casd2 registers will be unknown when the casen bit is set low. when the casen bit is set low, the casdi input path will be switched off and the casdo output will be foating.
rev. 1.00 58 july 19, 2017 rev. 1.00 59 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu ? caspre register bit 7 6 5 4 3 2 1 0 name caspre2 caspre1 caspre0 r/w r/w r/w r/w por 0 0 0 bit 7~3 unimplemented, read as "0" bit 2~0 caspre2~caspre0 : cascading transceiver clock f cas1 division ratio selection 000: f cas1 = f casclki 001: f cas1 = f casclki /2 010: f cas1 = f casclki /4 011: f cas1 = f casclki /8 100: f cas1 = f casclki /16 101: f cas1 = f casclki /32 110: f cas1 = f casclki /64 111: f cas1 = f casclki /128 these bits are used to select the cascading transceiver clock f cas1 division ratio. the f casclki clock is the cascading transceiver input clock which is sourced from the system clock f sys . the f cas1 clock is used to drive the whole cascading transceiver circuits except the reset time counter, rcnt. the reset time counter, rcnt, is driven by the clock, f cas2 , where f cas2 = f cas1 /16. ? casth register bit 7 6 5 4 3 2 1 0 name ths4 ths3 ths2 ths1 ths0 r/w r/w r/w r/w r/w r/w por 0 0 1 1 1 bit 7~5 unimplemented, read as "0" bit 4~0 ths4~ths0 : cascading transceiver rx function data judgment threshold t rx_dths t rx_dths = ths[4:0] t cas1 , where t cas1 = 1/f cas1 these bits are used to specify the cascading transceiver rx function input data judgment threshold value. when the input signal high level period is equal to or greater than the t rx_dths threshold, the input data will be recognized as a logic 1. however, the input data will be recognized as a logic 0 if the input signal high level period is less than the t rx_dths threshold. the received data will be stored in the casd0~casd2 registers. ? d0cnt register bit 7 6 5 4 3 2 1 0 name lcnt4 lcnt3 lcnt2 lcnt1 lcnt0 r/w r/w r/w r/w r/w r/w por 0 0 1 0 0 bit 7~5 unimplemented, read as "0" bit 4~0 lcnt4~lcnt0 : cascading transceiver tx function output data logic 0 high pulse count value, t tx_d0h t tx_d0h = lcnt[4:0] t cas1 , where t cas1 = 1/f cas1 these bits are used to specify the high pulse count value of the cascading transceiver tx function logic 0 output data, which is driven by the f cas1 clock. when the transmitted data stored in the casdn register is logic 0, a signal with a high pulse width of t tx_d0h and a low pulse width of (t bit - t tx_d0h ) will be output on the casdo line, where the bit time t bit is specified by the bit time counter pcnt. the lcnt feld minimum value should be properly confgured according to the corresponding cascading transceiv er input clock frequency, f casclki , for applications.
rev. 1.00 58 july 19, 2017 rev. 1.00 59 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu ? d1cnt register bit 7 6 5 4 3 2 1 0 name hcnt4 hcnt3 hcnt2 hcnt1 hcnt0 r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 bit 7~5 unimplemented, read as "0" bit 4~0 hcnt4~hcnt0 : cascading transceiver tx function output data logic 1 high pulse count value, t tx_d1h t tx_d1h = hcnt[4:0] t cas1 , where t cas1 = 1/f cas1 these bits are used to specify the high pulse count value of the cascading transceiver tx function logic 1 output data, which is driven by the f cas1 clock. when the transmitted data stored in the casdn register is logic 1, a signal with a high pulse width of t tx_d1h and a low pulse width of (t bit - t tx_d1h ) will be output on the casdo line, where the bit time t bit is specified by the bit time counter pcnt. the hcnt feld minimum value should be properly confgured according to the corresponding c ascading transceiver input clock frequency, f casclki , for applications. ? pcnt register bit 7 6 5 4 3 2 1 0 name ps 7 ps6 ps5 ps4 ps3 ps2 ps1 ps0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 1 1 0 0 0 bit 7~0 ps7~ps0 : cascading transceiver bit time counter t bit = ps[7:0] t cas1 , where t cas1 = 1/f cas1 this counter is used to specify the count value of the cascading transceiver data bit time period. the bit time counter is driven by the f cas1 clock. for the tx function the bit time counter is always enabled regardless of the pcnten bit status. in the tx mode the bit time is calculated as the above formula shown. when the trgtx bit is set to 1 in the tx mode, the pcnt and d0cnt or d1cnt counters will start to count. a signal with a high pulse of t tx_d0h or t tx_d1h and a low pulse of (t bit - t tx_d0h ) or (t bit - t tx_d1h ) representing a logic data 0 or 1 respectively will be output on the casdo line. for the rx function the bit time counter is also used to check whether the error condition on the received data occurs or not other than to specify the bit time. when the pcnt function is enabled by setting the pcnten bit high and there is a rising edge on the casdi line, the bit time counter pcnt will start to count down. if there is no second rising edge on the casdi line before the pcnt counter counts down to zero for the received data bit 0 ~ bit 22, the bit error fag, biterr, will automatically be set to 1, which means a bit transfer error occurs. for the data bit 23 reception if a falling edge appears on the casdi line before the pcnt counter counts down to zero, the rx shift register full fag, full24, will be set to 1. it means that the whole 24 bits data has been completely received. then the passen bit will automatically be set to 1 by hardware. if there is no falling edge on the casdi line when receiving the data bit 23 before the pcnt counter counts down to zero, the bit error fag, biterr, will also be set to 1 by hardware to indicate that a bit transfer error occurs. the passen bit will then be kept unchanged with a low level state.
rev. 1.00 60 july 19, 2017 rev. 1.00 61 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu ? rcnt register bit 7 6 5 4 3 2 1 0 name rs7 rs6 rs5 rs4 rs3 rs2 rs1 rs0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 0 0 0 0 0 0 0 bit 7~0 rs7~rs0 : cascading transceiver reset time counter t reset = rs[7:0] t cas2 , where t cas2 = 1/f cas2 = 16/f cas1 = 16 t cas1 this down-counter is used to specify the count value of the cascading transceiver reset time period in the rx function. the reset time counter is driven by the f cas2 clock where the f cas2 clock is equal to the f cas1 clock divided by 16. when the casmod bit is set to 0 to select the rx mode and the casen bit is set to 1 to enable the cascading transceiver function, the rcnt counter will start to count. if the casdi line signal is kept at a high or low level for a certain time period and the rcnt counts down to zero, the cascading transceiver reset fag, casres, will be set to 1 to indicate that a cascading transceiver reset condition occurs. when the casres bit is set to 1, the biterr, full24, passen bits will be cleared to 0 and the casrxen bit will be set to 1. ? casd0 register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 d7~d0 : data byte 0 this register is used to store the data byte 0 received in the rx mode or to be transmitted in the tx mode. ? casd1 register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 d7~d0 : data byte 1 this register is used to store the data byte 1 received in the rx mode or to be transmitted in the tx mode. ? casd2 register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 d7~d0 : data byte 2 this register is used to store the data byte 2 received in the rx mode or to be transmitted in the tx mode.
rev. 1.00 60 july 19, 2017 rev. 1.00 61 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu ? intcon register bit 7 6 5 4 3 2 1 0 name biterr casres empty24 full24 berinten resinten eptinten fulinten r/w r r r r r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 biterr : rx received data bit time out fag 0: no bit time-out error condition occurs 1: bit time-out error condition occurs the bit is used to indicate whether a received bit time-out condition occurs or not. when a received data bit time is greater than the t bit time specified by the pcnt register, the biterr bit will be set to 1 by hardware to indicate that a received bit time-out error condition occurs. when the bit time-out error condition occurs, the rx input data will not be decoded until the casres bit is set high which means that a cascading transceiver reset condition occurs. if the casres bit is set high, the biterr bit will automatically be cleared to 0 by hardware. bit 6 casres : cascading transceiver reset fag 0: no reset condition occurs 1: reset condition occurs the bit is used to indicate whether a cascading transceiver reset condition occurs or not. if the casdi line signal is kept unchanged at a high or low level for a certain time period greater than the t reset time specifed by the rcnt register, the casres bit will be set to 1 by hardware to indicate that a rx reset condition occurs. when the casres bit is set high, the biterr, full24 and passen bits will automatically be cleared to 0 and the casrxen bit will be set high by hardware. the casres bit will be cleared to 0 if a rising edge signal on the casdi line appears. bit 5 empty24 : cascading transceiver 24-bit tx shift register empty fag 0: tx shift register is not empty 1: tx shift register is empty the bit is used to indicate whether the cascading transceiver 24-bit tx shift register is empty or not. when the tx circuit transmits 24 bits data completely, the 24-bit shift register will be empty and the empty24 bit will be set to 1. if the empty24 bit is set high, the trgtx bit will automatically be cleared to 0 by hardware. when the trgtx bit is set high to initiate a transmission, the empty24 bit will automatically be cleared to 0. bit 4 full24 : cascading transceiver 24-bit rx shift register full fag 0: rx shift register is not full 1: rx shift register is full the bit is used to indicate whether the cascading transceiver 24-bit rx shift register is full or not. when the rx circuit receives 24 bits data completely, the 24-bit shift register will be full and the full24 bit will be set to 1. if the full24 bit is set high, the passen bit will be set to 1 and casrxen bit will be cleared to 0 by hardware. this makes that the casdi signal is directly output to the casdo line and bypassed the cascading transceiver. the full24 bit will automatically be cleared to 0 when the casres bit is set high. bit 3 berinten : rx received data bit error interrupt control 0: disable 1: enable the bit is used to control the rx received data bit error interrupt function. when the biterr bit is set high as the berinten bit is set high, the cascading transceiver will generate a bit error interrupt signal to inform the microcontroller.
rev. 1.00 62 july 19, 2017 rev. 1.00 63 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu bit 2 resinten : cascading transceiver reset interrupt control 0: disable 1: enable the bit is used to control the cascading transceiver reset interrupt function. when the casres bit is set high as the resinten bit is set high, the cascading transceiver will generate a reset interrupt signal to inform the microcontroller. bit 1 eptinten : cascading transceiver tx shift register empty interrupt control 0: disable 1: enable the bit is used to control the cascading transceiver tx shift register empty interrupt function. when the empty24 bit is set high as the eptinten bit is set high, the cascading transceiver will generate a tx shift register empty interrupt signal to inform the microcontroller. bit 0 fulinten : cascading transceiver rx shift register full interrupt control 0: disable 1: enable the bit is used to control the cascading transceiver rx shift register full interrupt function. when the full24 bit is set high as the fulinten bit is set high, the cascading transceiver will generate a rx shift register full interrupt signal to inform the microcontroller. cascade rx function operation the cascade rx function is used to decode the pulse from the casdi line to be logic high or logic low. cascade function logic high if the cascading transceiver clock high level count value is greater or equal than the rx function data judgment threshold value casth, it means logic high. casdi f cas1 pcnt_cnt 20 19 1 d n-1 data (to 8-bit shift register) dn=1 65 43 casth_cnt 7 7 6 1 0 2 19 18 17 16 20 14 15 13 12 11 10 8 9 6 4 5 7 falling edge, latch data, casth_cnt=0 data = 1 in rx mode (ex. casth= 7)
rev. 1.00 62 july 19, 2017 rev. 1.00 63 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu cascade function logic low if the cascading transceiver clock high level count value is less than the rx function data judgment threshold value casth, it means logic low. casdi f cas1 pcnt_cnt 20 19 0 d n-1 data (to 8-bit shift register) dn=0 65 43 casth_cnt 7 7 6 10 2 19 18 17 16 20 14 15 13 12 11 10 8 9 6 4 5 7 falling edge, latch data, casth_cnt>0 data = 0 in rx mode (ex. casth= 7) cascade rx procedure before cascade function is carried out, if the casdi line signal is kept at a high or low level for a certain time period and the rcnt counts down to zero, the cascading transceiver reset flag, casres, will be set to 1 to indicate that a cascading transceiver reset condition occurs. if the casres bit is set high, the bus for bypass (mux to casdo) will be disabled, it is only ready for the rx circuit to decode the casdi line signal. step 1: when master mcu resets the cascade single line bus, the full24, biterr and passen bits are cleared to 0, the casres and casrxen bits are set to 1, the rx circuit is only ready for the casdi line signal. step 2: when a rising edge appears on the casdi line, the rx circuit begins to count high level. if the high level count value is less than threshold casth value before a falling edge appears on the casdi line, it means logic low. if, the high level count value is greater or equal than threshold casth value before falling edge appears on the casdi line, it means logic high. step 3: when the 24 bits shift register is full, the full24 bit is set to 1, the bus is automatically enabled bypass path. so the passen bit is set to 1, and the casrxen bit is cleared to 0, the system will generate a casint interrupt. step 4: the input signal from casdi line will be transferred to casdo line through mux, and can be passed to the next device. step 5: when master mcu resets the cascade bus again, the process will begin from step1 again. step 6: when frst rising edge appears on the casdi line, the casres bit will be cleared to zero automatically. note : the cascade clock fcas1 can be adjusted for different baud rates.
rev. 1.00 64 july 19, 2017 rev. 1.00 65 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu biterr casdi f cas1 pcnt_cnt 1 d n-1 65 43 casth_cnt 7 1 0 2 19 18 17 16 20 14 15 13 12 11 10 8 9 6 4 5 7 falling edge, latch data, casth_cnt=0 3 1 2 0 data (to 8-bit shift register) dn bit error in rx mode for bit 0~bit 22 note: if there is no second rising edge on the casdi line before the pcnt counter counts down to zero for the received data bit 0 ~ bit 22, the bit error fag, biterr, will automatically be set to 1. d 23 casdi f cas1 pcnt_cnt d 22 65 43 casth_cnt 7 1 0 2 19 18 17 16 20 14 15 13 12 11 10 8 9 6 4 5 7 falling edge, latch data, casth_cnt>0 3 1 2 0 data (to 8-bit shift register) d 23=0 biterr full24 data = 0 in rx mode for bit 23 note: for the data bit 23 reception if a falling edge appears on the casdi line before the pcnt counter counts down to zero, the rx shift register full fag, full24, will be set to 1. before the casth counter counts down to zero, the data logic 0 will be read out when a falling edge appears on the casdi line.
rev. 1.00 64 july 19, 2017 rev. 1.00 65 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu d 23 casdi f cas1 pcnt_cnt d 22 65 43 casth_cnt 7 1 0 2 19 18 17 16 20 14 15 13 12 11 10 8 9 6 4 5 7 falling edge, latch data, casth_cnt=0 3 1 2 0 data (to 8-bit shift register) d 23=1 biterr full24 data = 1 in rx mode for bit 23 note: for the data bit 23 reception if a falling edge appears on the casdi line before the pcnt counter counts down to zero, the rx shift register full fag, full24, will be set to 1. when the casth counter counts down to zero, the data logic 1 will be stored in the 8-bit shift register and be read out until a falling edge appears on the casdi line. casdi f cas1 pcnt_cnt d 22 65 43 casth_cnt 7 10 2 19 18 17 16 20 14 15 13 12 11 10 8 9 6 4 5 7 3 1 2 0 data (to 8-bit shift register) biterr full24 20 note: this is an abnormal situation. if the casdi line signal is kept at a high level for the data bit 23 reception period. if no falling edge appears on the casdi line until the pcnt counter underflows, it means that the whole 24 bits data has not been completely received, the biterr bit will be set high, the full24 bit will be cleared to 0, and the passen bit will have no change.
rev. 1.00 66 july 19, 2017 rev. 1.00 67 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu cascade tx procedure step 1: firstly clear the casen bit to 0 to disable rx and tx functions. step 2: set the casmod bit high, and clear the passen bit to 0 to enable tx function and pass path to the tx circuit. then set the casen bit high. step 3: write value into the casd0, casd1, and casd2 registers step 4: set the trgtx bit high to begin to shift data in the casd0, casd1, and casd2 registers output. step 5: when the casint interrupt happened, fill value into the casd0, casd1, and casd2 registers again. repeat from step 4. step 6: when every n 24bits data shift out, the tx circuit can send a reset command to slave device, at that time, the rx circuit will set casres bit high by software. step 7: repeat from step 3 for next frame data (n 24bits) again. note : the cascade clock fcas1 can be adjusted for different baud rates. empty24 trgtx casdo f cas1 pcnt_cnt 98 76 d1cnt_cnt 10 43 5 15 14 13 12 16 10 11 9 21 0 4 5 2 0 1 3 16 dn 8 6 7 10 data = 1 in tx mode (n=0~22, d1cnt= 10) empty24 trgtx casdo f cas1 pcnt_cnt 32 10 d0cnt_cnt 4 4 15 14 13 12 16 10 11 9 4 5 2 0 1 3 16 dn 8 6 7 data = 0 in tx mode (n=0~22, d0cnt= 4)
rev. 1.00 66 july 19, 2017 rev. 1.00 67 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu empty24 trgtx casdo f cas1 pcnt_cnt 98 76 d1cnt_cnt 10 4 3 5 15 14 13 12 16 10 11 9 21 0 4 5 2 0 1 3 16 d23 8 6 7 10 data = 1 in tx mode (n=23, d1cnt= 10) note: the trgtx bit will be cleared to 0 by hardware when the tx shift register empty flag, empty24, is set high constant current led driver t here is an accurate constant current driver which is specifically designed for led display applications. the device provide s n-channel stable and constant current outputs for driving leds. the output constant current is determined by the current gain selection bits, ccg[1:0] and rgbn pwm input. the current variation between channels is less than 3% while the current variation between different devices is less than 6%. the characteristic curve in the saturation region is fat. the output current remains constant regardless of the led forward voltage value. the constant current can be calculated using the following formula: i ccon = 5ma gain if the ccen bit is set high and the rgbn signal is in a logic low level, the ccon is driven by a constant current. otherwise the ccon is in a foat ing status. regulator and dac ccon module 0 module n i out rgbn ccen vssn/3 vdd ccg[1:0] note: 1. n=0~2 2. module n stands for module 0 ~ module 2 3. vssn/3 stands for every 3 cco outputs sharing one vss. 4. rgbn is sourced from the compact type tm output ctpn. constant current led driver block diagram
rev. 1.00 68 july 19, 2017 rev. 1.00 69 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu ? ccs register bit 7 6 5 4 3 2 1 0 name ccen d6 d5 d4 ccg1 ccg0 r/w r/w r/w r/w r/w r/w r/w por 0 0 1 0 0 1 bit 7 ccen : constant current function enable or disable control 0: disable 1: enable if the ccen bit is set high and the rgbn signal is in a logic low level, the ccon is driven by a constant current. otherwise the ccon is in a foating status. bit 6~4 d6~d4 : reserved bits. these bits cannot be used and must be fxed as "010". bit 3~2 unimplemented, read as "0" bit 1~0 ccg1~ccg0 : constant current gain selection 00: gain= 1.0, i ccon =5ma 01: gain= 3.0 i ccon = 15 ma 10: gain= 7.0 , i ccon = 3 5ma 11: gain= 12.0 , i ccon =60ma
rev. 1.00 68 july 19, 2017 rev. 1.00 69 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu interrupts interrupts are an important part of any microcontroller system. when an external event or an internal function such as a timer module or an a/d converter requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. the device only contains internal interrupts functions. the internal interrupts are generated by various internal functions such as tms, time base, and cascading transceiver interface. interrupt registers overall interrupt control, which basically means the setting of request flags when certain microcontroller conditions occur and the setting of interrupt enable bits by the application program, is controlled by a series of registers, located in the special purpose data memory, as shown in the accompanying table. the frst is the intc0~ intc1 registers which setup the primary interrupts, the second is the mfi0~ mfi2 register s which setup the multi-function interrupts. each register contains a number of enable bits to enable or disable individual registers as well as interrupt flags to indicate the presence of an interrupt request. the naming convention of these follows a specifc pattern. first is listed an abbreviated interrupt type, then the (optional) number of that interrupt followed by either an "e" for enable/ disable bit or "f" for request fag. function enable bit request flag notes global emi multi-function mfne mfnf n=0~2 time base tbe tbf cascading transceiver interface casinte casintf ctm ctmnpe ctmnpf n=0~2 ctmnae ctmnaf interrupt register bit naming conventions register name bit 7 6 5 4 3 2 1 0 intc0 mf1f mf0f tbf mf1e mf0e tbe emi intc1 casintf mf2f casinte mf2e mfi0 ctm0af ctm0pf ctm0ae ctm0pe mfi1 ctm1af ctm1pf ctm1ae ctm1pe mfi2 ctm2af ctm2pf ctm2ae ctm2pe interrupt registers list ? intc0 register bit 7 6 5 4 3 2 1 0 name mf1f mf0f tbf mf1e mf0e tbe emi r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 unimplemented, read as "0" bit 6 mf1f : multi-function interrupt 1 request fag 0: no request 1: interrupt request bit 5 mf0f : multi-function interrupt 0 request fag 0: no request 1: interrupt request
rev. 1.00 70 july 19, 2017 rev. 1.00 71 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu bit 4 tbf : time base interrupt request fag 0: no request 1: interrupt request bit 3 mf1e : multi-function interrupt 1 control 0: disable 1: enable bit 2 mf0e : multi-function interrupt 0 control 0: disable 1: enable bit 1 tbe : time base interrupt control 0: disable 1: enable bit 0 emi : global interrupt control 0: disable 1: enable ? intc1 register bit 7 6 5 4 3 2 1 0 name casintf mf2f casinte mf2e r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~6 unimplemented, read as "0" bit 5 casintf : cascading transceiver interface interrupt request fag 0: no request 1: interrupt request bit 4 mf2f : multi-function interrupt 2 request fag 0: no request 1: interrupt request bit 3~2 unimplemented, read as "0" bit 1 casinte : cascading transceiver interface interrupt control 0: disable 1: enable bit 0 mf2e : multi-function interrupt control 0: disable 1: enable ? mfi0 register bit 7 6 5 4 3 2 1 0 name ctm0af ctm0pf ctm0ae ctm0pe r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~6 unimplemented, read as "0" bit 5 ctm0af : ctm comparator a match interrupt 0 request fag 0: no request 1: interrupt request bit 4 ctm0pf : ctm comparator p match interrupt 0 request fag 0: no request 1: interrupt request bit 3~2 unimplemented, read as "0"
rev. 1.00 70 july 19, 2017 rev. 1.00 71 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu bit 1 ctm0ae : ctm comparator a match interrupt 0 control 0: disable 1: enable bit 0 ctm0pe : ctm comparator p match interrupt 0 control 0: disable 1: enable ? mfi1 register bit 7 6 5 4 3 2 1 0 name ctm1af ctm1pf ctm1ae ctm1pe r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~6 unimplemented, read as "0" bit 5 ctm1af : ctm comparator a match interrupt 1 request fag 0: no request 1: interrupt request bit 4 ctm1pf : ctm comparator p match interrupt 1 request fag 0: no request 1: interrupt request bit 3~2 unimplemented, read as "0" bit 1 ctm1ae : ctm comparator a match interrupt 1 control 0: disable 1: enable bit 0 ctm1pe : ctm comparator p match interrupt 1 control 0: disable 1: enable ? mfi2 register bit 7 6 5 4 3 2 1 0 name ctm2af ctm2pf ctm2ae ctm2pe r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~6 unimplemented, read as "0" bit 5 ctm2af : ctm comparator a match interrupt 2 request fag 0: no request 1: interrupt request bit 4 ctm2pf : ctm comparator p match interrupt 2 request fag 0: no request 1: interrupt request bit 3~2 unimplemented, read as "0" bit 1 ctm2ae : ctm comparator a match interrupt 2 control 0: disable 1: enable bit 0 ctm2pe : ctm comparator p match interrupt 2 control 0: disable 1: enable
rev. 1.00 72 july 19, 2017 rev. 1.00 73 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu interrupt operation when the conditions for an interrupt event occur, such as a tm comparator p or comparator a match etc., the relevant interrupt request fag will be set. whether the request fag actually generates a program jump to the relevant interrupt vector is determined by the condition of the interrupt enable bit. if the enable bit is set high then the program will jump to its relevant vector, if the enable bit is zero then although the interrupt request fag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector. the global interrupt enable bit, if cleared to zero, will disable all interrupts. when an interrupt is generated, the program counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. the program counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. the microcontroller will then fetch its next instruction from this interrupt vector. the instruction at this vector will usually be a "jmp" which will jump to another section of program which is known as the interrupt service routine. here is located the code to control the appropriate interrupt. the interrupt service routine must be terminated with a "reti", which retrieves the original program counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. the various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagrams with their order of priority. some interrupt sources have their own individual vector while others share the same multi-function interrupt vector. once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the global interrupt enable bit, emi bit will be cleared automatically. this will prevent any further interrupt nesting from occurring. however, if other interrupt requests occur during this interval, although the interrupt will not be immediately serviced, the request fag will still be recorded. if an interrupt requires immediate servicing while the program is already in another interrupt service routine, the emi bit should be set after entering the routine, to allow interrupt nesting. if the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. if immediate service is desired, the stack must be prevented from becoming full. in case of simultaneous requests, the accompanying diagram shows the priority that is applied. all of the interrupt request f ags when set will wake-up the device if it is in sleep or idle mode, however to prevent a wake-up from occurring the corresponding fag should be set before the device is in sleep or idle mode.
rev. 1.00 72 july 19, 2017 rev. 1.00 73 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu interrupt name request flags enable bits master enable vector emi auto disabled in isr priority high low interrupts contained within multi-function interrupts xxe enable bits xxf request flag, auto reset in isr legend xxf request flag, no auto reset in isr m. funct. 0 mf0f mf0e emi emi m. funct. 1 mf1f mf1e 08h 0ch ctm0 p ctm0pf ctm0pe ctm0 a ctm0af ctm0ae ctm1 p ctm1pf ctm1pe ctm1 a ctm1af ctm1ae 04h emi cascade transceiver casintf casinte emi 14h interrupt name request flags enable bits time base tbf tbe emi m. funct. 2 mf2f mf2e 10h ctm2 p ctm2pf ctm2pe ctm2 a ctm2af ctm2ae interrupt scheme multi-function interrupt within the device there are three multi-function interrupts. unlike the other independent interrupts, the interrupt has no independent source, but rather are formed from other existing interrupt sources, namely the tm interrupt. a multi-function interrupt request will take place when any of the multi-function interrupt request fag mfnf is set. the multi-function interrupt fag will be set when any of their included functions generate an interrupt request fag. to allow the program to branch to its respective interrupt vector address, when the multi-function interrupt is enabled and the stack is not full, and either one of the interrupts contained within each of multi-function interrupt occurs, a subroutine call to one of the multi-function interrupt vectors will take place. when the interrupt is serviced, the related multi- function request fag will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. however, it must be noted that, although the multi-function interrupt request flags will be automatically reset when the interrupt is serviced, the request flags from the original source of the multi-function interrupt will not be automatically reset and must be manually reset by the application program. time base interrupt the function of the time base interrupt is to provide regular time signal in the form of an internal interrupt. it is controlled by the overflow signal from its internal timer. when this happens its interrupt request fag, tbf, will be set. to allow the program to branch to its respective interrupt vector addresses, the global interrupt enable bit, emi and time base enable bit, tbe, must frst be set. when the interrupt is enabled, the stack is not full and the time base overfows, a subroutine call to its respective vector location will take place. when the interrupt is serviced, the interrupt request flag, tbf, will be automatically reset and the emi bit will be cleared to disable other interrupts.
rev. 1.00 74 july 19, 2017 rev. 1.00 75 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu the purpose of the time base interrupt is to provide an interrupt signal at fxed time periods. its clock source, f psc , originates from the internal clock source f sys , f sys /4 or f sub and then passes through a divider, the division ratio of which is selected by programming the appropriate bits in the tbc register to obtain longer interrupt periods whose value ranges. the clock source which in turn controls the time base interrupt period is selected using the clksel [1:0] in the pscr register respectively. f sys /4 f sys f sub m u x prescaler clksel[1:0] f psc f psc /2 8 ~ f psc /2 15 m u x tb[2:0] time base interrupt tbon time base interrupt ? pscr register bit 7 6 5 4 3 2 1 0 name clksel1 clksel0 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 clksel1~clksel0 : prescaler clock source selection 00: f sys 01: f sys /4 1x: f sub ? tbc register bit 7 6 5 4 3 2 1 0 name tbon tb2 tb1 tb0 r/w r/w r/w r/w r/w por 0 0 0 0 bit 7 tbon : time base enable control 0: disable 1: enable bit 6~3 unimplemented, read as "0" bit 2~0 tb2~tb0 : time base time-out period selection 000: 2 8 /f psc 001: 2 9 /f psc 010: 2 10 /f psc 011: 2 11 /f psc 100: 2 12 /f psc 101: 2 13 /f psc 110: 2 14 /f psc 111: 2 15 /f psc
rev. 1.00 74 july 19, 2017 rev. 1.00 75 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu cascade transceiver interface interrupt a cascade transceiver interface interrupt request will take place when the cascade transceiver interface interrupt request fag, casintf, is set, which occurs when rx receive data format error , cascade circuit reset, cascading transceiver tx shift register is empty, or cascading transceiver rx shift register is full. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and the cascade transceiver interface interrupt enable bit, casinte, must frst be set. when the interrupt is enabled, the stack is not full and the above four described situations occur, a subroutine call to the respective interrupt vector , will take place. when the cascade transceiver interface interrupt is serviced, the interrupt request fag, casintf, will be automatically reset and the emi bit will be cleared to disable other interrupts. timer module interrupts the ctm has two interrupts which are both contained within the multi-function interrupt. for the ctm there are two interrupt request fags ctmnpf and ctmnaf and two enable bits ctmnpe and ctmnae. a ctm interrupt request will take place when any of the ctm request fags is set, a situation which occurs when a ctm comparator p or comparator a match situation happens. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and the respective ctm interrupt enable bit, and the associated multi-function interrupt enable bit, mfnf, must frst be set. when the interrupt is enabled, the stack is not full and a ctm comparator match situation occurs, a subroutine call to the relevant ctm interrupt vector locations, will take place. when the ctm interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the related mfnf fag will be automatically cleared. as the ctm interrupt request fags will not be automatically cleared, they have to be cleared by the application program. interrupt wake-up function each of the interrupt functions has the capability of waking up the microcontroller when in the sleep or idle mode. a wake-up is generated when an interrupt request fag changes from low to high and is independent of whether the interrupt is enabled or not. care must therefore be taken if spurious wake-up situations are to be avoided. if an interrupt wake-up function is to be disabled then the corresponding interrupt request fag should be set high before the device enters the sleep or idle mode. the interrupt enable bits have no effect on the interrupt wake-up function.
rev. 1.00 76 july 19, 2017 rev. 1.00 77 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu programming considerations by disabling the relevant interrupt enable bits, a requested interrupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request fag is cleared by the application program. where a certain interrupt is contained within a multi-function interrupt, then when the interrupt service routine is executed, as only the multi-function interrupt request flags, mfnf, will be automatically cleared, the individual request flag for the function needs to be cleared by the application program. it is recommended that programs do not use the "call" instruction within the interrupt service subroutine. interrupts often occur in an unpredictable manner or need to be serviced immediately. if only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged once a call subroutine is executed in the interrupt subroutine. every interrupt has the capability of waking up the microcontroller when it is in sleep or idle mode, the wake up being generated when the interrupt request fag changes from low to high. if it is required to prevent a certain interrupt from waking up the microcontroller then its respective request fag should be frst set high before enter sleep or idle mode. as only the program counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator, status register or other registers are altered by the interrupt service program, their contents should be saved to the memory at the beginning of the interrupt service routine. to return from an interrupt subroutine, either a ret or reti instruction may be executed. the reti instruction in addition to executing a return to the main program also automatically sets the emi bit high to allow further interrupts. the ret instruction however only executes a return to the main program leaving the emi bit in its present zero state and therefore disabling the execution of further interrupts.
rev. 1.00 76 july 19, 2017 rev. 1.00 77 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu application circuits 104 2.2v~5.5v vss vdd timer module timer module timer module pa5/cco0 pa6/cco1 pa7/cco2 gpio ht8 mcu core constant current pa0/icpda 2.2v~5.5v cascading transceiver pa3/casdi pa4/casdo pa2/icpck/casdi pa1/casdo
rev. 1.00 78 july 19, 2017 rev. 1.00 79 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. in the case of holtek microcontroller, a comprehensive and fexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. for easier understanding of the various instruction codes, they have been subdivided into several functional groupings. instruction timing most instructions are implemented within one instruction cycle. the exceptions to this are branch, call, or table read instructions where two instruction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator, most instructions would be implemented within 0.5s and branch or call instructions would be implemented within 1s. although instructions which require one more cycle to implement are generally limited to the jmp, call, ret, reti and table read instructions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to implement. as instructions which change the contents of the pcl will imply a direct jump to that new address, one more cycle will be required. examples of such instructions would be "clr pcl" or "mov pcl, a". for the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the transfer of data within the microcontroller program is one of the most frequently used operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specifc immediate data directly into the accumulator. one of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. within the holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specifed.
rev. 1.00 78 july 19, 2017 rev. 1.00 79 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu logical and rotate operation the standard logical operations such as and, or, xor and cpl all have their own instruction within the holtek microcontroller instruction set. as with the case of most instructions involving data manipulation, data must pass through the accumulator which may involve additional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. different rotate instructions exist depending on program requirements. rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the carry bit from where it can be examined and the necessary serial bit set high or low. another application which rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specifed locations using the jmp instruction or to a subroutine using the call instruction. they differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. this is done by placing a return instruction "ret" in the subroutine which will cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping off point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is frst made regarding the condition of a certain data memory or individual bits. depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. these instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits. bit operations the ability to provide single bit operations on data memory is an extremely fexible feature of all holtek microcontrollers. this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the "set [m].i" or "clr [m]. i" instructions respectively. the feature removes the need for programmers to frst read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write process is taken care of automatically when these bit operation instructions are used. table read operations data storage is normally implemented by using registers. however, when working with large amounts of fxed data, the volume involved often makes it inconvenient to store the fxed data in the data memory. to overcome this problem, holtek microcontrollers allow an area of program memory to be set as a table where data can be directly stored. a set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the "halt" instruction for power-down operations and instructions to control the operation of the watchdog timer for reliable program operations under extreme electric or electromagnetic environments. for their relevant operations, refer to the functional related sections.
rev. 1.00 80 july 19, 2017 rev. 1.00 81 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. table conventions x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a,[m] add data memory to acc 1 z, c, ac, ov addm a,[m] add acc to data memory 1 note z, c, ac, ov add a,x add immediate data to acc 1 z, c, ac, ov adc a,[m] add data memory to acc with carry 1 z, c, ac, ov adcm a,[m] add acc to data memory with carry 1 note z, c, ac, ov sub a,x subtract immediate data from the acc 1 z, c, ac, ov sub a,[m] subtract data memory from acc 1 z, c, ac, ov subm a,[m] subtract data memory from acc with result in data memory 1 note z, c, ac, ov sbc a,[m] subtract data memory from acc with carry 1 z, c, ac, ov sbcm a,[m] subtract data memory from acc with carry, result in data memory 1 note z, c, ac, ov daa [m] decimal adjust acc for addition with result in data memory 1 note c logic operation and a,[m] logical and data memory to acc 1 z or a,[m] logical or data memory to acc 1 z xor a,[m] logical xor data memory to acc 1 z andm a,[m] logical and acc to data memory 1 note z orm a,[m] logical or acc to data memory 1 note z xorm a,[m] logical xor acc to data memory 1 note z and a,x logical and immediate data to acc 1 z or a,x logical or immediate data to acc 1 z xor a,x logical xor immediate data to acc 1 z cpl [m] complement data memory 1 note z cpla [m] complement data memory with result in acc 1 z increment & decrement inca [m] increment data memory with result in acc 1 z inc [m] increment data memory 1 note z deca [m] decrement data memory with result in acc 1 z dec [m] decrement data memory 1 note z rotate rra [m] rotate data memory right with result in acc 1 none rr [m] rotate data memory right 1 note none rrca [m] rotate data memory right through carry with result in acc 1 c rrc [m] rotate data memory right through carry 1 note c rla [m] rotate data memory left with result in acc 1 none rl [m] rotate data memory left 1 note none rlca [m] rotate data memory left through carry with result in acc 1 c rlc [m] rotate data memory left through carry 1 note c
rev. 1.00 80 july 19, 2017 rev. 1.00 81 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu mnemonic description cycles flag affected data move mov a,[m] move data memory to acc 1 none mov [m],a move acc to data memory 1 note none mov a,x move immediate data to acc 1 none bit operation clr [m].i clear bit of data memory 1 note none set [m].i set bit of data memory 1 note none branch operation jmp addr jump unconditionally 2 none sz [m] skip if data memory is zero 1 note none sza [m] skip if data memory is zero with data movement to acc 1 note none sz [m].i skip if bit i of data memory is zero 1 note none snz [m].i skip if bit i of data memory is not zero 1 note none siz [m] skip if increment data memory is zero 1 note none sdz [m] skip if decrement data memory is zero 1 note none siza [m] skip if increment data memory is zero with result in acc 1 note none sdza [m] skip if decrement data memory is zero with result in acc 1 note none call addr subroutine call 2 none ret return from subroutine 2 none ret a,x return from subroutine and load immediate data to acc 2 none reti return from interrupt 2 none table read operation tabrd [m] read table (specifc page) to tblh and data memory 2 note none tabrdc [m] read table (current page) to tblh and data memory 2 note none tabrdl [m] read table (last page) to tblh and data memory 2 note none miscellaneous nop no operation 1 none clr [m] clear data memory 1 note none set [m] set data memory 1 note none clr wdt clear watchdog timer 1 to, pdf clr wdt1 pre-clear watchdog timer 1 to, pdf clr wdt2 pre-clear watchdog timer 1 to, pdf swap [m] swap nibbles of data memory 1 note none swapa [m] swap nibbles of data memory with result in acc 1 none halt enter power down mode 1 to, pdf note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the "clr wdt1" and "clr wdt2" instructions the to and pdf flags may be affected by the execution status. the to and pdf flags are cleared after both "clr wdt1" and "clr wdt2" instructions are consecutively executed. otherwise the to and pdf fags remain unchanged.
rev. 1.00 82 july 19, 2017 rev. 1.00 83 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu instruction defnition adc a,[m] add data memory to acc with carry description the contents of the specifed data memory, accumulator and the carry fag are added. the result is stored in the accumulator. operation acc acc + [m] + c affected fag(s) ov, z, ac, c adcm a,[m] add acc to data memory with carry description the contents of the specifed data memory, accumulator and the carry fag are added. the result is stored in the specifed data memory. operation [m] acc + [m] + c affected fag(s) ov, z, ac, c add a,[m] add data memory to acc description the contents of the specifed data memory and the accumulator are added. the result is stored in the accumulator. operation acc acc + [m] affected fag(s) ov, z, ac, c add a,x add immediate data to acc description the contents of the accumulator and the specifed immediate data are added. the result is stored in the accumulator. operation acc acc + x affected fag(s) ov, z, ac, c addm a,[m] add acc to data memory description the contents of the specifed data memory and the accumulator are added. the result is stored in the specifed data memory. operation [m] acc + [m] affected fag(s) ov, z, ac, c and a,[m] logical and data memory to acc description data in the accumulator and the specifed data memory perform a bitwise logical and operation. the result is stored in the accumulator. operation acc acc and [m] affected fag(s) z and a,x logical and immediate data to acc description data in the accumulator and the specifed immediate data perform a bit wise logical and operation. the result is stored in the accumulator. operation acc acc and x affected fag(s) z andm a,[m] logical and acc to data memory description data in the specifed data memory and the accumulator perform a bitwise logical and operation. the result is stored in the data memory. operation [m] acc and [m] affected fag(s) z
rev. 1.00 82 july 19, 2017 rev. 1.00 83 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu call addr subroutine call description unconditionally calls a subroutine at the specifed address. the program counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. the specifed address is then loaded and the program continues execution from this new address. as this instruction requires an additional operation, it is a two cycle instruction. operation stack program counter + 1 program counter addr affected fag(s) none clr [m] clear data memory description each bit of the specifed data memory is cleared to 0. operation [m] 00h affected fag(s) none clr [m].i clear bit of data memory description bit i of the specifed data memory is cleared to 0. operation [m].i 0 affected fag(s) none clr wdt clear watchdog timer description the to, pdf fags and the wdt are all cleared. operation wdt cleared to 0 pdf 0 affected fag(s) to, pdf clr wdt1 pre-clear watchdog timer description the to, pdf fags and the wdt are all cleared. note that this instruction works in conjunction with clr wdt2 and must be executed alternately with clr wdt2 to have effect. repetitively executing this instruction without alternately executing clr wdt2 will have no effect. operation wdt cleared to 0 pdf 0 affected fag(s) to, pdf clr wdt2 pre-clear watchdog timer description the to, pdf fags and the wdt are all cleared. note that this instruction works in conjunction with clr wdt1 and must be executed alternately with clr wdt1 to have effect. repetitively executing this instruction without alternately executing clr wdt1 will have no effect. operation wdt cleared to 0 pdf 0 affected fag(s) to, pdf cpl [m] complement data memory description each bit of the specifed data memory is logically complemented (1s complement). bits which previously contained a 1 are changed to 0 and vice versa. operation [m] [m] affected fag(s) z
rev. 1.00 84 july 19, 2017 rev. 1.00 85 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu cpla [m] complement data memory with result in acc description each bit of the specifed data memory is logically complemented (1s complement). bits which previously contained a 1 are changed to 0 and vice versa. the complemented result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc [m] affected fag(s) z daa [m] decimal-adjust acc for addition with result in data memory description convert the contents of the accumulator value to a bcd (binary coded decimal) value resulting from the previous addition of two bcd variables. if the low nibble is greater than 9 or if ac fag is set, then a value of 6 will be added to the low nibble. otherwise the low nibble remains unchanged. if the high nibble is greater than 9 or if the c fag is set, then a value of 6 will be added to the high nibble. essentially, the decimal conversion is performed by adding 00h, 06h, 60h or 66h depending on the accumulator and fag conditions. only the c fag may be affected by this instruction which indicates that if the original bcd sum is greater than 100, it allows multiple precision decimal addition. operation [m] acc + 00h or [m] acc + 06h or [m] acc + 60h or [m] acc + 66h affected fag(s) c dec [m] decrement data memory description data in the specifed data memory is decremented by 1. operation [m] [m] ? 1 affected fag(s) z deca [m] decrement data memory with result in acc description data in the specifed data memory is decremented by 1. the result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc [m] ? 1 affected fag(s) z halt enter power down mode description this instruction stops the program execution and turns off the system clock. the contents of the data memory and registers are retained. the wdt and prescaler are cleared. the power down fag pdf is set and the wdt time-out fag to is cleared. operation to 0 pdf 1 affected fag(s) to, pdf inc [m] increment data memory description data in the specifed data memory is incremented by 1. operation [m] [m] + 1 affected fag(s) z inca [m] increment data memory with result in acc description data in the specifed data memory is incremented by 1. the result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc [m] + 1 affected fag(s) z
rev. 1.00 84 july 19, 2017 rev. 1.00 85 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu jmp addr jump unconditionally description the contents of the program counter are replaced with the specifed address. program execution then continues from this new address. as this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. operation program counter addr affected fag(s) none mov a,[m] move data memory to acc description the contents of the specifed data memory are copied to the accumulator. operation acc [m] affected fag(s) none mov a,x move immediate data to acc description the immediate data specifed is loaded into the accumulator. operation acc x affected fag(s) none mov [m],a move acc to data memory description the contents of the accumulator are copied to the specifed data memory. operation [m] acc affected fag(s) none nop no operation description no operation is performed. execution continues with the next instruction. operation no operation affected fag(s) none or a,[m] logical or data memory to acc description data in the accumulator and the specifed data memory perform a bitwise logical or operation. the result is stored in the accumulator. operation acc acc or [m] affected fag(s) z or a,x logical or immediate data to acc description data in the accumulator and the specifed immediate data perform a bitwise logical or operation. the result is stored in the accumulator. operation acc acc or x affected fag(s) z orm a,[m] logical or acc to data memory description data in the specifed data memory and the accumulator perform a bitwise logical or operation. the result is stored in the data memory. operation [m] acc or [m] affected fag(s) z ret return from subroutine description the program counter is restored from the stack. program execution continues at the restored address. operation program counter stack affected fag(s) none
rev. 1.00 86 july 19, 2017 rev. 1.00 87 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu ret a,x return from subroutine and load immediate data to acc description the program counter is restored from the stack and the accumulator loaded with the specifed immediate data. program execution continues at the restored address. operation program counter stack acc x affected fag(s) none reti return from interrupt description the program counter is restored from the stack and the interrupts are re-enabled by setting the emi bit. emi is the master interrupt global enable bit. if an interrupt was pending when the reti instruction is executed, the pending interrupt routine will be processed before returning to the main program. operation program counter stack emi 1 affected fag(s) none rl [m] rotate data memory left description the contents of the specifed data memory are rotated left by 1 bit with bit 7 rotated into bit 0. operation [m].(i+1) [m].i; (i=0~6) [m].0 [m].7 affected fag(s) none rla [m] rotate data memory left with result in acc description the contents of the specifed data memory are rotated left by 1 bit with bit 7 rotated into bit 0. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; (i=0~6) acc.0 [m].7 affected fag(s) none rlc [m] rotate data memory left through carry description the contents of the specifed data memory and the carry fag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry fag is rotated into bit 0. operation [m].(i+1) [m].i; (i=0~6) [m].0 c c [m].7 affected fag(s) c rlca [m] rotate data memory left through carry with result in acc description data in the specifed data memory and the carry fag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry fag is rotated into the bit 0. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; (i=0~6) acc.0 c c [m].7 affected fag(s) c rr [m] rotate data memory right description the contents of the specifed data memory are rotated right by 1 bit with bit 0 rotated into bit 7. operation [m].i [m].(i+1); (i=0~6) [m].7 [m].0 affected fag(s) none
rev. 1.00 86 july 19, 2017 rev. 1.00 87 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu rra [m] rotate data memory right with result in acc description data in the specifed data memory is rotated right by 1 bit with bit 0 rotated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i=0~6) acc.7 [m].0 affected fag(s) none rrc [m] rotate data memory right through carry description the contents of the specifed data memory and the carry fag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry fag is rotated into bit 7. operation [m].i [m].(i+1); (i=0~6) [m].7 c c [m].0 affected fag(s) c rrca [m] rotate data memory right through carry with result in acc description data in the specifed data memory and the carry fag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry fag is rotated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i=0~6) acc.7 c c [m].0 affected fag(s) c sbc a,[m] subtract data memory from acc with carry description the contents of the specifed data memory and the complement of the carry fag are subtracted from the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. operation acc acc ? [m] ? c affected fag(s) ov, z, ac, c sbcm a,[m] subtract data memory from acc with carry and result in data memory description the contents of the specifed data memory and the complement of the carry fag are subtracted from the accumulator. the result is stored in the data memory. note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. operation [m] acc ? [m] ? c affected fag(s) ov, z, ac, c sdz [m] skip if decrement data memory is 0 description the contents of the specifed data memory are frst decremented by 1. if the result is 0 the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m] ? 1 skip if [m]=0 affected fag(s) none
rev. 1.00 88 july 19, 2017 rev. 1.00 89 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu sdza [m] skip if decrement data memory is zero with result in acc description the contents of the specifed data memory are frst decremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specifed data memory contents remain unchanged. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation acc [m] ? 1 skip if acc=0 affected fag(s) none set [m] set data memory description each bit of the specifed data memory is set to 1. operation [m] ffh affected fag(s) none set [m].i set bit of data memory description bit i of the specifed data memory is set to 1. operation [m].i 1 affected fag(s) none siz [m] skip if increment data memory is 0 description the contents of the specifed data memory are frst incremented by 1. if the result is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m] + 1 skip if [m]=0 affected fag(s) none siza [m] skip if increment data memory is zero with result in acc description the contents of the specifed data memory are frst incremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specifed data memory contents remain unchanged. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m] + 1 skip if acc=0 affected fag(s) none snz [m].i skip if bit i of data memory is not 0 description if bit i of the specifed data memory is not 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is 0 the program proceeds with the following instruction. operation skip if [m].i 0 affected fag(s) none sub a,[m] subtract data memory from acc description the specifed data memory is subtracted from the contents of the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. operation acc acc ? [m] affected fag(s) ov, z, ac, c
rev. 1.00 88 july 19, 2017 rev. 1.00 89 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu subm a,[m] subtract data memory from acc with result in data memory description the specifed data memory is subtracted from the contents of the accumulator. the result is stored in the data memory. note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. operation [m] acc ? [m] affected fag(s) ov, z, ac, c sub a,x subtract immediate data from acc description the immediate data specifed by the code is subtracted from the contents of the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. operation acc acc ? x affected fag(s) ov, z, ac, c swap [m] swap nibbles of data memory description the low-order and high-order nibbles of the specifed data memory are interchanged. operation [m].3~[m].0 ? [m].7~[m].4 affected fag(s) none swapa [m] swap nibbles of data memory with result in acc description the low-order and high-order nibbles of the specifed data memory are interchanged. the result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc.3~acc.0 [m].7~[m].4 acc.7~acc.4 [m].3~[m].0 affected fag(s) none sz [m] skip if data memory is 0 description if the contents of the specifed data memory is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation skip if [m]=0 affected fag(s) none sza [m] skip if data memory is 0 with data movement to acc description the contents of the specifed data memory are copied to the accumulator. if the value is zero, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m] skip if [m]=0 affected fag(s) none sz [m].i skip if bit i of data memory is 0 description if bit i of the specifed data memory is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation skip if [m].i=0 affected fag(s) none
rev. 1.00 90 july 19, 2017 rev. 1.00 91 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu tabrd [m] read table (specifc page) to tblh and data memory description the low byte of the program code (specifc page) addressed by the table pointer pair (tbhp and tblp) is moved to the specifed data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected fag(s) none tabrdc [m] read table (current page) to tblh and data memory description the low byte of the program code (current page) addressed by the table pointer (tblp) is moved to the specifed data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected fag(s) none tabrdl [m] read table (last page) to tblh and data memory description the low byte of the program code (last page) addressed by the table pointer (tblp) is moved to the specifed data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected fag(s) none xor a,[m] logical xor data memory to acc description data in the accumulator and the specifed data memory perform a bitwise logical xor operation. the result is stored in the accumulator. operation acc acc xor [m] affected fag(s) z xorm a,[m] logical xor acc to data memory description data in the specifed data memory and the accumulator perform a bitwise logical xor operation. the result is stored in the data memory. operation [m] acc xor [m] affected fag(s) z xor a,x logical xor immediate data to acc description data in the accumulator and the specifed immediate data perform a bitwise logical xor operation. the result is stored in the accumulator. operation acc acc xor x affected fag(s) z
rev. 1.00 90 july 19, 2017 rev. 1.00 91 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu package information note that the package information provided here is for consultation purposes only. as this information may be updated at regular intervals users are reminded to consult the holtek website for the latest version of the package/carton information . additional supplementary information with regard to packaging is listed below. click on the relevant section to be transferred to the relevant website page. ? further package information (include outline dimensions, product tape and reel specifcations) ? packing meterials information ? carton information
rev. 1.00 92 july 19, 2017 rev. 1.00 93 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu 8-pin sop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0.236 bsc b 0.154 bsc c 0.012 0.020 c 0.193 bsc d 0.069 e 0.050 bsc f 0.004 0.010 g 0.016 0.050 h 0.004 0.010 0 8 symbol dimensions in mm min. nom. max. a 6 bsc b 3.9 bsc c 0.31 0.51 c 4.9 bsc d 1.75 e 1.27 bsc f 0.10 0.25 g 0.40 1.27 h 0.10 0.25 0 8
rev. 1.00 92 july 19, 2017 rev. 1.00 93 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu 8-pin dfn (2mm3mm) outline dimensions e d l e2 k 5 1 8 4 d2 e b a1 a3 a symbol dimensions in inch min. nom. max. a 0.028 0.030 0.031 a1 0.000 0.001 0.002 a3 0.080 bsc b 0.008 0.010 0.012 d 0.079 bsc e 0.118 bsc e 0.020 bsc d2 0.047 0.051 0.053 e2 0.051 0.055 0.057 l 0.012 0.014 0.016 k 0.008 symbol dimensions in mm min. nom. max. a 0.700 0.750 0.800 a1 0.000 0.020 0.050 a3 0.200 bsc b 0.200 0.250 0.300 d 2.000 bsc e 3.000 bsc e 0.500 bsc d2 1.200 1.300 1.350 e2 1.300 1.400 1.450 l 0.315 0.365 0.415 k 0.200
rev. 1.00 94 july 19, 2017 rev. 1.00 95 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu 10-pin sop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0.236 bsc b 0.154 bsc c 0.012 0.018 c 0.193 bsc d 0.069 e 0.039 bsc f 0.004 0.010 g 0.016 0.050 h 0.004 0.010 0 8 symbol dimensions in mm min. nom. max. a 6.00 bsc b 3.90 bsc c 0.30 0.45 c 4.90 bsc d 1.75 e 1.00 bsc f 0.10 0.25 g 0.40 1.27 h 0.10 0.25 0 8
rev. 1.00 94 july 19, 2017 rev. 1.00 95 july 19, 2017 HT45F0060 rgb dimming led flash mcu HT45F0060 rgb dimming led flash mcu copyright ? 2017 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek assumes no responsibility arising from the use of the specifcations described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek's products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notifcation. for the most up-to-date information, please visit our web site at http://www.holtek.com/en/.

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